CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.asm.rpt
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.cdf
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.done
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.fit.rpt
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.fit.smsg
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.fit.summary
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.flow.rpt
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.map.rpt
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.map.smsg
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.map.summary
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.pin
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.pof
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.qpf
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.qsf
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.sof
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.sta.rpt
CD1_EDGE_DECT/FPGA_CODE/CD1_EDGE_DECT.sta.summary
CD1_EDGE_DECT/FPGA_CODE/greybox_tmp/cbx_args.txt
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/AUDIO_DAC.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/CD1_EDGE_DECT.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/CMOS_Capture.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Curve_Averaging.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/I2C_Controller.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/I2C_OV5620_Config.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/lcd_display.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Line_Buffer.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/MAC_3.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/mif/osd.mif
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/mif/OV_DISP.mif
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/mif/vip.mif
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/osd_rom.qip
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/osd_rom.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/PLL.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/RAW2RGB.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Reset_Delay.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/RGB2Mono.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/command.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/control_interface.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/Sdram_Control_4Port.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/Sdram_Params.h
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/Sdram_PLL.bsf
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/Sdram_PLL.ppf
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/Sdram_PLL.qip
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/Sdram_PLL.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/Sdram_RD_FIFO.qip
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/Sdram_RD_FIFO.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/Sdram_WR_FIFO.qip
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/Sdram_WR_FIFO.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port/sdr_data_path.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sobel/center.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sobel/LineBuffer_3.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sobel/MAC_sobel.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sobel/PA_3.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sobel/Sobel.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sobel/SQRT.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/TP_RAM.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/VGA_Ctrl.v
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/vip_rom.qip
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/vip_rom.v
CD1_EDGE_DECT/FPGA_CODE/osd_rom.qip
CD1_EDGE_DECT/FPGA_CODE/PLLJ_PLLSPE_INFO.txt
CD1_EDGE_DECT/FPGA_CODE/Sdram_PLL.qip
CD1_EDGE_DECT/FPGA_CODE/Sdram_RD_FIFO.qip
CD1_EDGE_DECT/Reference/Edge Detection Reference.pdf
CD1_EDGE_DECT/Reference/matlab边缘检测/1.jpg
CD1_EDGE_DECT/Reference/matlab边缘检测/lena.bmp
CD1_EDGE_DECT/Reference/matlab边缘检测/lenaOutput.jpg
CD1_EDGE_DECT/Reference/matlab边缘检测/sobel.m
CD1_EDGE_DECT/Reference/matlab边缘检测/sobel2.m
CD1_EDGE_DECT/Reference/sobel.pdf
CD1_EDGE_DECT/Reference/sobel_edge.c
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/mif
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sdram_Control_4Port
CD1_EDGE_DECT/FPGA_CODE/MY_CODE/Sobel
CD1_EDGE_DECT/FPGA_CODE/greybox_tmp
CD1_EDGE_DECT/FPGA_CODE/MY_CODE
CD1_EDGE_DECT/Reference/matlab边缘检测
CD1_EDGE_DECT/FPGA_CODE
CD1_EDGE_DECT/Reference
CD1_EDGE_DECT