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文件名称:emif

  • 所属分类：
    嵌入式/单片机编程
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2015-03-24
  • 文件大小：
    2.97mb
  • 已下载：
    0次
  • 提 供 者：
    lotustila
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

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configure for emif-fpga
相关搜索： emif

(系统自动生成,下载前可以参看下载内容)

下载文件列表

压缩包 : code.zip 列表
Design/
Design/Extra/
Design/Extra/CoregenFifo/
Design/Extra/CoregenFifo/CoreGen/
Design/Extra/CoregenFifo/CoreGen/coregen.prj
Design/Extra/CoregenFifo/CoreGen/fifo_511x32.edn
Design/Extra/CoregenFifo/CoreGen/fifo_511x32.vhd
Design/Extra/CoregenFifo/CoreGen/fifo_511x32.vho
Design/Extra/CoregenFifo/CoreGen/fifo_511x32.xco
Design/Extra/CoregenFifo/CoreGen/fifo_511x32.xcp
Design/Extra/CoregenFifo/CoreGen/fifo_511x32_flist.txt
Design/Extra/CoregenFifo/Documentation/
Design/Extra/CoregenFifo/Documentation/async_fifo.pdf
Design/Extra/CoregenFifo/Documentation/EMIF fifo with CoreGen Modules.ppt
Design/Extra/CoregenFifo/Synthesis/
Design/Extra/CoregenFifo/Synthesis/EmifCoreGenFifo.prd
Design/Extra/CoregenFifo/Synthesis/EmifCoreGenFifo.prj
Design/Extra/CoregenFifo/Synthesis/Pres/
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo.psp
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/EmifCoreGenFifo.edf
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/EmifCoreGenFifo.ucf
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/EmifCoreGenFifo.xdb
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/EmifCoreGenFifo_area.rep
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/EmifCoreGenFifo_area_info.sdc
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/EmifCoreGenFifo_constraints.sdc
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/EmifCoreGenFifo_fsm.rep
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/EmifCoreGenFifo_impl_1.psi
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/EmifCoreGenFifo_rtl.ixdb
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/EmifCoreGenFifo_timing.rep
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/fsm_work/
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/fsm_work/fsm.log
Design/Extra/CoregenFifo/Synthesis/Pres/EmifCoreGenFifo_impl_1/precision.log
Design/Extra/CoregenFifo/Synthesis/Pres/precision.log
Design/Extra/CoregenFifo/Synthesis/rev_1/
Design/Extra/CoregenFifo/Synthesis/rev_1/.recordref
Design/Extra/CoregenFifo/Synthesis/rev_1/EmifCoreGenFifo.edf
Design/Extra/CoregenFifo/Synthesis/rev_1/EmifCoreGenFifo.fse
Design/Extra/CoregenFifo/Synthesis/rev_1/EmifCoreGenFifo.ncf
Design/Extra/CoregenFifo/Synthesis/rev_1/EmifCoreGenFifo.srd
Design/Extra/CoregenFifo/Synthesis/rev_1/EmifCoreGenFifo.srm
Design/Extra/CoregenFifo/Synthesis/rev_1/EmifCoreGenFifo.srr
Design/Extra/CoregenFifo/Synthesis/rev_1/EmifCoreGenFifo.srs
Design/Extra/CoregenFifo/Synthesis/rev_1/EmifCoreGenFifo.tlg
Design/Extra/CoregenFifo/Synthesis/rev_1/syntmp/
Design/Extra/CoregenFifo/Synthesis/rev_1/syntmp/EmifCoreGenFifo.plg
Design/Extra/CoregenFifo/Vhdl/
Design/Extra/CoregenFifo/Vhdl/EmifCoreGenFifo.vhd
Design/Extra/LargeSelfAddrFifo/
Design/Extra/LargeSelfAddrFifo/Documentation/
Design/Extra/LargeSelfAddrFifo/Documentation/Large Self Addressing Fifo.ppt
Design/Extra/LargeSelfAddrFifo/Simscripts/
Design/Extra/LargeSelfAddrFifo/Simscripts/LargeSelfAddrFifoComp.do
Design/Extra/LargeSelfAddrFifo/Simscripts/LargeSelfAddrFifoDat.vec
Design/Extra/LargeSelfAddrFifo/Simscripts/LargeSelfAddrFifoWave.do
Design/Extra/LargeSelfAddrFifo/Vhdl/
Design/Extra/LargeSelfAddrFifo/Vhdl/GrayCnt4b.vhd
Design/Extra/LargeSelfAddrFifo/Vhdl/LargeSelfAddrFifo.vhd
Design/Extra/LargeSelfAddrFifo/Vhdl/LargeSelfAddrFifo_TestBench.vhd
Design/Extra/LargeSelfAddrFifo/Vhdl/LargeSelfAddrFifo_Tester.vhd
Design/Ise/
Design/Ise/AltEmifInt/
Design/Ise/AltEmifInt/AltEmifInt.bld
Design/Ise/AltEmifInt/AltEmifInt.cel
Design/Ise/AltEmifInt/AltEmifInt.mrp
Design/Ise/AltEmifInt/AltEmifInt.ncd
Design/Ise/AltEmifInt/AltEmifInt.ngd
Design/Ise/AltEmifInt/AltEmifInt.ngm
Design/Ise/AltEmifInt/AltEmifInt.npl
Design/Ise/AltEmifInt/AltEmifInt.par
Design/Ise/AltEmifInt/AltEmifInt.pcf
Design/Ise/AltEmifInt/AltEmifInt.twr
Design/Ise/AltEmifInt/AltEmifInt_pad.txt
Design/ReadMe.txt
Design/Simscripts/
Design/Simscripts/AltEmifIntComp.do
Design/Simscripts/AltEmifIntDat.vec
Design/Simscripts/AltEmifIntWave.do
Design/Simulation/
Design/Simulation/vsim.wlf
Design/Simulation/work/
Design/Simulation/work/altemifint/
Design/Simulation/work/altemifint/altemifint_arch.asm
Design/Simulation/work/altemifint/altemifint_arch.dat
Design/Simulation/work/altemifint/_primary.dat
Design/Simulation/work/altemifint_testbench/
Design/Simulation/work/altemifint_testbench/altemifint_struct.asm
Design/Simulation/work/altemifint_testbench/altemifint_struct.dat
Design/Simulation/work/altemifint_testbench/_primary.dat
Design/Simulation/work/altemifint_tester/
Design/Simulation/work/altemifint_tester/altemifint_flow.asm
Design/Simulation/work/altemifint_tester/altemifint_flow.dat
Design/Simulation/work/altemifint_tester/_primary.dat
Design/Simulation/work/_info
Design/Synthesis/
Design/Synthesis/Emif.psp
Design/Synthesis/EmifInterface.prd
Design/Synthesis/EmifInterface.prj
Design/Synthesis/precision.log
Design/Synthesis/rev_1/
Design/Synthesis/rev_1/.recordref
Design/Synthesis/rev_1/AltEmifInt.edf
Design/Synthesis/rev_

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