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文件名称:Design_and_Test_VerilogHDL

  • 所属分类：
    VHDL编程
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2008-10-13
  • 文件大小：
    1.8mb
  • 已下载：
    0次
  • 提 供 者：
    Z***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码，很多使用的实例，并有说明，是学习Verilog 不可多得的好资料。
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Example-2-1/HelloVlog.v
Example-3-1/FullAdd.v
Example-3-1/transcript
Example-3-2/FullAdd.v
Example-3-3/CRC10.v
Example-4-1/cnt.prd
Example-4-1/cnt.prj
Example-4-1/rev_1/cnt1.edf
Example-4-1/rev_1/cnt1.fse
Example-4-1/rev_1/cnt1.srm
Example-4-1/rev_1/cnt1.srr
Example-4-1/rev_1/cnt1.srs
Example-4-1/rev_1/cnt1.tlg
Example-4-1/rev_1/cnt2.edf
Example-4-1/rev_1/cnt2.fse
Example-4-1/rev_1/cnt2.srm
Example-4-1/rev_1/cnt2.srr
Example-4-1/rev_1/cnt2.srs
Example-4-1/rev_1/cnt2.tlg
Example-4-1/rev_1/cnt3.edf
Example-4-1/rev_1/cnt3.fse
Example-4-1/rev_1/cnt3.srm
Example-4-1/rev_1/cnt3.srr
Example-4-1/rev_1/cnt3.srs
Example-4-1/rev_1/cnt3.tlg
Example-4-1/rev_1/syntmp/cnt1.plg
Example-4-1/rev_1/syntmp/cnt2.msg
Example-4-1/rev_1/syntmp/cnt2.plg
Example-4-1/rev_1/syntmp/cnt3.msg
Example-4-1/rev_1/syntmp/cnt3.plg
Example-4-1/source/cnt1.v
Example-4-1/source/cnt2.v
Example-4-1/source/cnt3.v
Example-4-1/source/syntmp.msg
Example-4-1/示例说明.doc
Example-4-4/reg_counter.prd
Example-4-4/reg_counter.prj
Example-4-4/reg_counter.v
Example-4-4/rev_2/reg_counter.edf
Example-4-4/rev_2/reg_counter.fse
Example-4-4/rev_2/reg_counter.ncf
Example-4-4/rev_2/reg_counter.srd
Example-4-4/rev_2/reg_counter.srm
Example-4-4/rev_2/reg_counter.srr
Example-4-4/rev_2/reg_counter.srs
Example-4-4/rev_2/reg_counter.tlg
Example-4-4/rev_2/rpt_reg_counter.areasrr
Example-4-4/rev_2/rpt_reg_counter_areasrr.htm
Example-4-4/rev_2/syntmp/reg_counter.msg
Example-4-4/rev_2/syntmp/reg_counter.plg
Example-4-4/rev_2/verif/reg_counter.vif
Example-4-4/sim/reg_counter.v
Example-4-4/source/reg_counter.v
Example-4-4/示例说明.doc
Example-4-7/clock_edge.prd
Example-4-7/clock_edge.prj
Example-4-7/clock_edge.v
Example-4-7/rev_2/clock_edge.edn
Example-4-7/rev_2/clock_edge.fse
Example-4-7/rev_2/clock_edge.prf
Example-4-7/rev_2/clock_edge.srm
Example-4-7/rev_2/clock_edge.srr
Example-4-7/rev_2/clock_edge.srs
Example-4-7/rev_2/clock_edge.tlg
Example-4-7/rev_2/generic.fse
Example-4-7/rev_2/generic.srd
Example-4-7/rev_2/syntmp/clock_edge.msg
Example-4-7/rev_2/syntmp/clock_edge.plg
Example-4-7/sim/clock_edge.v
Example-4-7/sim/clock_edge_tb.v
Example-4-7/sim/sim_clock_edge.cr.mti
Example-4-7/sim/sim_clock_edge.mpf
Example-4-7/sim/transcript
Example-4-7/sim/vsim.wlf
Example-4-7/sim/wave.do
Example-4-7/sim/work/_info
Example-4-7/sim/work/clock_edge/_primary.dat
Example-4-7/sim/work/clock_edge/_primary.vhd
Example-4-7/sim/work/clock_edge/verilog.asm
Example-4-7/sim/work/clock_edge_tb/_primary.dat
Example-4-7/sim/work/clock_edge_tb/_primary.vhd
Example-4-7/sim/work/clock_edge_tb/verilog.asm
Example-4-7/source/clock_edge.v
Example-4-7/source/clock_edge_tb.v
Example-4-7/syntmp.msg
Example-4-7/示例说明.doc
Example-4-8/decode_cmb.prd
Example-4-8/decode_cmb.prj
Example-4-8/decode_cmb.v
Example-4-8/decode_cmb2.v
Example-4-8/rev_2/decode_cmb.edn
Example-4-8/rev_2/decode_cmb.fse
Example-4-8/rev_2/decode_cmb.prf
Example-4-8/rev_2/decode_cmb.srm
Example-4-8/rev_2/decode_cmb.srr
Example-4-8/rev_2/decode_cmb.srs
Example-4-8/rev_2/decode_cmb.tlg
Example-4-8/rev_2/decode_cmb2.edn
Example-4-8/rev_2/decode_cmb2.fse
Example-4-8/rev_2/decode_cmb2.prf
Example-4-8/rev_2/decode_cmb2.srm
Example-4-8/rev_2/decode_cmb2.srr
Example-4-8/rev_2/decode_cmb2.srs
Example-4-8/rev_2/decode_cmb2.tlg
Example-4-8/rev_2/generic.fse
Example-4-8/rev_2/generic.srd
Example-4-8/rev_2/syntmp/decode_cmb.plg
Example-4-8/rev_2/syntmp/decode_cmb2.msg
Example-4-8/rev_2/syntmp/decode_cmb2.plg
Example-4-8/sim/decode_cmb.cr.mti
Example-4-8/sim/decode_cmb.mpf
Example-4-8/sim/decode_cmb.v
Example-4-8/sim/decode_cmb2.v
Example-4-8/sim/decode_cmb_tb.v
Example-4-8/sim/transcript
Example-4-8/sim/vsim.wlf
Example-4-8/sim/work/_info
Example-4-8/sim/work/decode_cmb/_primary.dat
Example-4-8/sim/work/decode_cmb/_primary.vhd
Example-4-8/sim/work/decode_cmb/verilog.asm
Example-4-8/sim/work/decode_cmb2/_primary.dat
Example-4-8/sim/work/decode_cmb2/_primary.vhd
Example-4-8/sim/work/decode_cmb2/verilog.asm
Example-4-8/sim/work/decode_cmb_tb/_primary.dat
Example-4-8/sim/work/decode_cmb_tb/_primary.vhd
Example-4-8/sim/work/decode_cmb_tb/verilog.asm
Example-4-8/source/decode_cmb.v
Example-4-8/source/decode_cmb2.v
Example-4-8/source/decode_cmb_tb.v
Example-4-8/示例说明.doc
Example-4-10/bibus/bibus.prd
Example-4-10/bibus/bibus.prj
Example-4-10/bibus/bibus.v
Example-4-10/bibus/decode.v
Example-4-10/bibus/rev_1/bibus.fse
Example-4-10/bibus/rev_1/bibus.srd
Example-4-10/bibus/rev_1/bibus.srm
Example-4-10/bibus/rev_1/bibus.srr
Example-4-10/bibus/rev_1/bibus.srs
Example-4-10/bibus/rev_1/bibus.sxr
Example-4-10/bibus/rev_1/bibus.tcl
Example-4-10/bibus/rev_1/bibus.tlg
Example-4-10/bibus/rev_1/bibus.vqm
Example-4-10/bibus/rev_1/bibus.xrf
Example-4-10/bibus/rev_1/bibus_cons.tcl
Example-4-10/bibus/rev_1/bibus_rm.tcl
Example-4-10/bibus/rev_1/rpt_bibus.areasrr
Example-4-10/bibus/rev_1/rpt_bibus_areasrr.htm
Example-4-10/bibus/rev_1/syntmp/bibus.msg
Example-4-10/bibus/rev_1/syntmp/bibus.plg
Example-4-10/bibus/rev_1/syntmp/bibus_cons_ui.tcl
Example-4-10/bibus/rev_1/verif/bibus.vif
Example-4-10/bibus/syntmp.msg
Example-4-10/complex_bibus/complex_bibus.prd
Example-4-10/complex_bibus/complex_bibus.prj
Example-4

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