文件名称:DDR2-verilog
-
所属分类:
- 标签属性:
- 上传时间:2015-07-19
-
文件大小:1.42mb
-
已下载:1次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
ddr2的Verilog代码,包括时序控制,数据读取,利用verilog编写的ddr2控制器,在spartan6板子上得以验证,成功实现了FPGA与DDR2的通信。-ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the FPGA and DDR2 communications.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DDR2-verilog/
DDR2-verilog/Params.v
DDR2-verilog/altclklock.v
DDR2-verilog/chart/
DDR2-verilog/chart/ͼ9-16.bmp
DDR2-verilog/chart/ͼ9-17.bmp
DDR2-verilog/chart/ͼ9-19.bmp
DDR2-verilog/chart/ͼ9-20.bmp
DDR2-verilog/chart/ͼ9-22.bmp
DDR2-verilog/chart/ͼ9-23.bmp
DDR2-verilog/chart/ͼ9-26.bmp
DDR2-verilog/chart/ͼ9-27.bmp
DDR2-verilog/ddr.cr.mti
DDR2-verilog/ddr.mpf
DDR2-verilog/ddr_Command.v
DDR2-verilog/ddr_control_interface.v
DDR2-verilog/ddr_data_path.v
DDR2-verilog/ddr_sdram.v
DDR2-verilog/ddr_sdram_tb.v
DDR2-verilog/note.txt
DDR2-verilog/pll1.v
DDR2-verilog/transcript
DDR2-verilog/vsim.wlf
DDR2-verilog/wave/
DDR2-verilog/wave/ddr_command.bmp
DDR2-verilog/wave/ddr_control_interface.bmp
DDR2-verilog/wave/ddr_data_path.bmp
DDR2-verilog/wave/ddr_sdram.bmp
DDR2-verilog/wave/ddr_sdram_tb.bmp
DDR2-verilog/work/
DDR2-verilog/work/_info
DDR2-verilog/work/altclklock/
DDR2-verilog/work/altclklock/_primary.dat
DDR2-verilog/work/altclklock/_primary.vhd
DDR2-verilog/work/altclklock/verilog.asm
DDR2-verilog/work/ddr_command/
DDR2-verilog/work/ddr_command/_primary.dat
DDR2-verilog/work/ddr_command/_primary.vhd
DDR2-verilog/work/ddr_command/verilog.asm
DDR2-verilog/work/ddr_control_interface/
DDR2-verilog/work/ddr_control_interface/_primary.dat
DDR2-verilog/work/ddr_control_interface/_primary.vhd
DDR2-verilog/work/ddr_control_interface/verilog.asm
DDR2-verilog/work/ddr_data_path/
DDR2-verilog/work/ddr_data_path/_primary.dat
DDR2-verilog/work/ddr_data_path/_primary.vhd
DDR2-verilog/work/ddr_data_path/verilog.asm
DDR2-verilog/work/ddr_sdram/
DDR2-verilog/work/ddr_sdram/_primary.dat
DDR2-verilog/work/ddr_sdram/_primary.vhd
DDR2-verilog/work/ddr_sdram/verilog.asm
DDR2-verilog/work/ddr_sdram_tb/
DDR2-verilog/work/ddr_sdram_tb/_primary.dat
DDR2-verilog/work/ddr_sdram_tb/_primary.vhd
DDR2-verilog/work/ddr_sdram_tb/verilog.asm
DDR2-verilog/work/mt46v4m16/
DDR2-verilog/work/mt46v4m16/_primary.dat
DDR2-verilog/work/mt46v4m16/_primary.vhd
DDR2-verilog/work/mt46v4m16/verilog.asm
DDR2-verilog/work/pll1/
DDR2-verilog/work/pll1/_primary.dat
DDR2-verilog/work/pll1/_primary.vhd
DDR2-verilog/work/pll1/transcript
DDR2-verilog/work/pll1/verilog.asm
DDR2-verilog/Params.v
DDR2-verilog/altclklock.v
DDR2-verilog/chart/
DDR2-verilog/chart/ͼ9-16.bmp
DDR2-verilog/chart/ͼ9-17.bmp
DDR2-verilog/chart/ͼ9-19.bmp
DDR2-verilog/chart/ͼ9-20.bmp
DDR2-verilog/chart/ͼ9-22.bmp
DDR2-verilog/chart/ͼ9-23.bmp
DDR2-verilog/chart/ͼ9-26.bmp
DDR2-verilog/chart/ͼ9-27.bmp
DDR2-verilog/ddr.cr.mti
DDR2-verilog/ddr.mpf
DDR2-verilog/ddr_Command.v
DDR2-verilog/ddr_control_interface.v
DDR2-verilog/ddr_data_path.v
DDR2-verilog/ddr_sdram.v
DDR2-verilog/ddr_sdram_tb.v
DDR2-verilog/note.txt
DDR2-verilog/pll1.v
DDR2-verilog/transcript
DDR2-verilog/vsim.wlf
DDR2-verilog/wave/
DDR2-verilog/wave/ddr_command.bmp
DDR2-verilog/wave/ddr_control_interface.bmp
DDR2-verilog/wave/ddr_data_path.bmp
DDR2-verilog/wave/ddr_sdram.bmp
DDR2-verilog/wave/ddr_sdram_tb.bmp
DDR2-verilog/work/
DDR2-verilog/work/_info
DDR2-verilog/work/altclklock/
DDR2-verilog/work/altclklock/_primary.dat
DDR2-verilog/work/altclklock/_primary.vhd
DDR2-verilog/work/altclklock/verilog.asm
DDR2-verilog/work/ddr_command/
DDR2-verilog/work/ddr_command/_primary.dat
DDR2-verilog/work/ddr_command/_primary.vhd
DDR2-verilog/work/ddr_command/verilog.asm
DDR2-verilog/work/ddr_control_interface/
DDR2-verilog/work/ddr_control_interface/_primary.dat
DDR2-verilog/work/ddr_control_interface/_primary.vhd
DDR2-verilog/work/ddr_control_interface/verilog.asm
DDR2-verilog/work/ddr_data_path/
DDR2-verilog/work/ddr_data_path/_primary.dat
DDR2-verilog/work/ddr_data_path/_primary.vhd
DDR2-verilog/work/ddr_data_path/verilog.asm
DDR2-verilog/work/ddr_sdram/
DDR2-verilog/work/ddr_sdram/_primary.dat
DDR2-verilog/work/ddr_sdram/_primary.vhd
DDR2-verilog/work/ddr_sdram/verilog.asm
DDR2-verilog/work/ddr_sdram_tb/
DDR2-verilog/work/ddr_sdram_tb/_primary.dat
DDR2-verilog/work/ddr_sdram_tb/_primary.vhd
DDR2-verilog/work/ddr_sdram_tb/verilog.asm
DDR2-verilog/work/mt46v4m16/
DDR2-verilog/work/mt46v4m16/_primary.dat
DDR2-verilog/work/mt46v4m16/_primary.vhd
DDR2-verilog/work/mt46v4m16/verilog.asm
DDR2-verilog/work/pll1/
DDR2-verilog/work/pll1/_primary.dat
DDR2-verilog/work/pll1/_primary.vhd
DDR2-verilog/work/pll1/transcript
DDR2-verilog/work/pll1/verilog.asm
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.