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文件名称:FIFO_POLL

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  • 上传时间:
    2015-07-20
  • 文件大小:
    2.25mb
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    0次
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DSP通过EMIF接口访问FPGA内部寄存器(FD6713开发板)-DSP access the internal registers in FPGA via EMIF interface (FD6713 Development Board)
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FIFO_POLL/DSP/boot_c671x.h62
FIFO_POLL/DSP/boot_c671x.s62
FIFO_POLL/DSP/c6713_emif.s62
FIFO_POLL/DSP/cc_build_Debug.log
FIFO_POLL/DSP/csl6713.lib
FIFO_POLL/DSP/Debug/boot_c671x.obj
FIFO_POLL/DSP/Debug/c6713_emif.obj
FIFO_POLL/DSP/Debug/FIFO.map
FIFO_POLL/DSP/Debug/FIFO.out
FIFO_POLL/DSP/Debug/main.obj
FIFO_POLL/DSP/Debug.lkf
FIFO_POLL/DSP/Debug.lkv
FIFO_POLL/DSP/dsk6713.cmd
FIFO_POLL/DSP/dsp67x.lib
FIFO_POLL/DSP/FBConfig1.cdd
FIFO_POLL/DSP/FBTC6713.out
FIFO_POLL/DSP/FIFO.paf
FIFO_POLL/DSP/FIFO.pjt
FIFO_POLL/DSP/hex6x.exe
FIFO_POLL/DSP/main.c
FIFO_POLL/DSP/out2hex.bat
FIFO_POLL/DSP/out2hex.cmd
FIFO_POLL/FPGA/emif.bgn
FIFO_POLL/FPGA/emif.bit
FIFO_POLL/FPGA/emif.bld
FIFO_POLL/FPGA/emif.cmd_log
FIFO_POLL/FPGA/emif.drc
FIFO_POLL/FPGA/emif.gise
FIFO_POLL/FPGA/emif.lso
FIFO_POLL/FPGA/emif.ncd
FIFO_POLL/FPGA/emif.ngc
FIFO_POLL/FPGA/emif.ngd
FIFO_POLL/FPGA/emif.ngr
FIFO_POLL/FPGA/emif.ntrc_log
FIFO_POLL/FPGA/emif.pad
FIFO_POLL/FPGA/emif.par
FIFO_POLL/FPGA/emif.pcf
FIFO_POLL/FPGA/emif.prj
FIFO_POLL/FPGA/emif.ptwx
FIFO_POLL/FPGA/emif.restore
FIFO_POLL/FPGA/emif.stx
FIFO_POLL/FPGA/emif.syr
FIFO_POLL/FPGA/emif.twr
FIFO_POLL/FPGA/emif.twx
FIFO_POLL/FPGA/emif.ucf
FIFO_POLL/FPGA/emif.unroutes
FIFO_POLL/FPGA/emif.ut
FIFO_POLL/FPGA/emif.v
FIFO_POLL/FPGA/emif.xise
FIFO_POLL/FPGA/emif.xpi
FIFO_POLL/FPGA/emif.xst
FIFO_POLL/FPGA/emif_bitgen.xwbt
FIFO_POLL/FPGA/emif_envsettings.html
FIFO_POLL/FPGA/emif_guide.ncd
FIFO_POLL/FPGA/emif_map.map
FIFO_POLL/FPGA/emif_map.mrp
FIFO_POLL/FPGA/emif_map.ncd
FIFO_POLL/FPGA/emif_map.ngm
FIFO_POLL/FPGA/emif_map.xrpt
FIFO_POLL/FPGA/emif_ngdbuild.xrpt
FIFO_POLL/FPGA/emif_pad.csv
FIFO_POLL/FPGA/emif_pad.txt
FIFO_POLL/FPGA/emif_par.xrpt
FIFO_POLL/FPGA/emif_prev_built.ngd
FIFO_POLL/FPGA/emif_summary.html
FIFO_POLL/FPGA/emif_summary.xml
FIFO_POLL/FPGA/emif_usage.xml
FIFO_POLL/FPGA/emif_xdb/cst.xbcd
FIFO_POLL/FPGA/emif_xst.xrpt
FIFO_POLL/FPGA/fifo_generator_ug175.pdf
FIFO_POLL/FPGA/icon.asy
FIFO_POLL/FPGA/icon.cdc
FIFO_POLL/FPGA/icon.ncf
FIFO_POLL/FPGA/icon.ngc
FIFO_POLL/FPGA/icon.v
FIFO_POLL/FPGA/icon.veo
FIFO_POLL/FPGA/icon.vhd
FIFO_POLL/FPGA/icon.vho
FIFO_POLL/FPGA/icon.xco
FIFO_POLL/FPGA/icon_flist.txt
FIFO_POLL/FPGA/icon_xmdf.tcl
FIFO_POLL/FPGA/ila.asy
FIFO_POLL/FPGA/ILA.cdc
FIFO_POLL/FPGA/ila.ncf
FIFO_POLL/FPGA/ila.ngc
FIFO_POLL/FPGA/ila.v
FIFO_POLL/FPGA/ila.veo
FIFO_POLL/FPGA/ila.vhd
FIFO_POLL/FPGA/ila.vho
FIFO_POLL/FPGA/ila.xco
FIFO_POLL/FPGA/ila_flist.txt
FIFO_POLL/FPGA/ila_xmdf.tcl
FIFO_POLL/FPGA/interface.ut
FIFO_POLL/FPGA/ipafifo.asy
FIFO_POLL/FPGA/ipafifo.ngc
FIFO_POLL/FPGA/ipafifo.sym
FIFO_POLL/FPGA/ipafifo.v
FIFO_POLL/FPGA/ipafifo.veo
FIFO_POLL/FPGA/ipafifo.vhd
FIFO_POLL/FPGA/ipafifo.vho
FIFO_POLL/FPGA/ipafifo.xco
FIFO_POLL/FPGA/ipafifo_fifo_generator_v4_3_xst_1.lso
FIFO_POLL/FPGA/ipafifo_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
FIFO_POLL/FPGA/ipafifo_fifo_generator_v4_3_xst_1_vhdl.prj
FIFO_POLL/FPGA/ipafifo_flist.txt
FIFO_POLL/FPGA/ipafifo_ngdbuild.xrpt
FIFO_POLL/FPGA/ipafifo_readme.txt
FIFO_POLL/FPGA/ipafifo_xmdf.tcl
FIFO_POLL/FPGA/ipafifo_xst.xrpt
FIFO_POLL/FPGA/iseconfig/emif.projectmgr
FIFO_POLL/FPGA/iseconfig/emif.xreport
FIFO_POLL/FPGA/Schematic1.sch
FIFO_POLL/FPGA/Schematic1.schlog
FIFO_POLL/FPGA/templates/coregen.xml
FIFO_POLL/FPGA/test.txt
FIFO_POLL/FPGA/top.jhd
FIFO_POLL/FPGA/top.sch
FIFO_POLL/FPGA/top.schlog
FIFO_POLL/FPGA/top.v
FIFO_POLL/FPGA/Untitled.mcs
FIFO_POLL/FPGA/Untitled.prm
FIFO_POLL/FPGA/Untitled.sig
FIFO_POLL/FPGA/usage_statistics_webtalk.html
FIFO_POLL/FPGA/webtalk.log
FIFO_POLL/FPGA/webtalk_pn.xml
FIFO_POLL/FPGA/xlnx_auto_0.ise
FIFO_POLL/FPGA/xlnx_auto_0_xdb/cst.xbcd
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/version
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/common/regkeys
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/regkeys
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/STE/netgen/regkeys
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/STE/ngcbuild/regkeys
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/STE/regkeys
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/STE/xst/regkeys
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise.lock
FIFO_POLL/FPGA/xst/work/hdllib.ref
FIFO_POLL/FPGA/xst/work/vlg09/icon.bin
FIFO_POLL/FPGA/xst/work/vlg2E/ipafifo.bin
FIFO_POLL/FPGA/xst/work/vlg3E/ila.bin
FIFO_POLL/FPGA/xst/work/vlg69/emif.bin
FIFO_POLL/FPGA/_impact.cmd
FIFO_POLL/FPGA/_impact.log
FIFO_POLL/FPGA/_ngo/netlist.lst
FIFO_POLL/FPGA/_xmsgs/bitgen.xmsgs
FIFO_POLL/FPGA/_xmsgs/map.xmsgs
FIFO_POLL/FPGA/_xmsgs/ngdbuild.xmsgs
FIFO_POLL/FPGA/_xmsgs/par.xmsgs
FIFO_POLL/FPGA/_xmsgs/pn_parser.xmsgs
FIFO_POLL/FPGA/_xmsgs/trce.xmsgs
FIFO_POLL/FPGA/_xmsgs/xst.xmsgs
FIFO_POLL/FPGA/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject
FIFO_PO

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