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文件名称:flappybird

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2015-08-25
  • 文件大小：
    2.16mb
  • 已下载：
    0次
  • 提 供 者：
    w****
  • 相关连接：
    无
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这是我练手时写的一个小游戏，是基于flappybird游戏原理制作的，用硬件完成其功能。主要用Verilog语言完成功能描述，通过ps2键盘的空格键控制飞翔，在VGA上进行显示。本工程已在basys2实验开发板上进行验证，画面略显粗糙，见谅。-This is what I wrote when practiced hand of a little game, is based on the principle of making flappybird game, with the hardware perform its function. Verilog language used to complete the main functional descr iption, by ps2 keyboard spacebar to control fly, display on VGA. This project has been validated in basys2 experimental development board, the picture slightly rough, sorry
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ps2_vga_ver2/
ps2_vga_ver2/_ngo/
ps2_vga_ver2/_ngo/netlist.lst
ps2_vga_ver2/_xmsgs/
ps2_vga_ver2/_xmsgs/bitgen.xmsgs
ps2_vga_ver2/_xmsgs/map.xmsgs
ps2_vga_ver2/_xmsgs/ngdbuild.xmsgs
ps2_vga_ver2/_xmsgs/par.xmsgs
ps2_vga_ver2/_xmsgs/pn_parser.xmsgs
ps2_vga_ver2/_xmsgs/trce.xmsgs
ps2_vga_ver2/_xmsgs/xst.xmsgs
ps2_vga_ver2/fuse.log
ps2_vga_ver2/fuse.xmsgs
ps2_vga_ver2/fuseRelaunch.cmd
ps2_vga_ver2/ipcore_dir/
ps2_vga_ver2/ipcore_dir/_xmsgs/
ps2_vga_ver2/ipcore_dir/_xmsgs/cg.xmsgs
ps2_vga_ver2/ipcore_dir/_xmsgs/pn_parser.xmsgs
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/blk_mem_gen_v7_2_readme.txt
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/doc/
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/doc/blk_mem_gen_v7_2_vinfo.html
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/doc/pg058-blk-mem-gen.pdf
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/example_design/
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/example_design/blk_mem_gen_v7_2_exdes.ucf
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/example_design/blk_mem_gen_v7_2_exdes.vhd
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/example_design/blk_mem_gen_v7_2_exdes.xdc
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/example_design/blk_mem_gen_v7_2_prod.vhd
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/implement/
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/implement/implement.bat
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/implement/implement.sh
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/implement/planAhead_ise.bat
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/implement/planAhead_ise.sh
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/implement/planAhead_ise.tcl
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/implement/xst.prj
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/implement/xst.scr
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/addr_gen.vhd
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/blk_mem_gen_v7_2_synth.vhd
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/blk_mem_gen_v7_2_tb.vhd
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/bmg_stim_gen.vhd
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/bmg_tb_pkg.vhd
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/simcmds.tcl
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/simulate_isim.bat
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/simulate_mti.bat
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/simulate_mti.do
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/simulate_mti.sh
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/simulate_ncsim.sh
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/simulate_vcs.sh
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/ucli_commands.key
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/vcs_session.tcl
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/wave_mti.do
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/functional/wave_ncsim.sv
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/random.vhd
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/simcmds.tcl
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/simulate_isim.bat
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/simulate_mti.bat
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/simulate_mti.do
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/simulate_mti.sh
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/simulate_ncsim.sh
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/simulate_vcs.sh
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/ucli_commands.key
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/vcs_session.tcl
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/wave_mti.do
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2/simulation/timing/wave_ncsim.sv
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2.asy
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2.gise
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2.mif
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2.ngc
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2.sym
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2.v
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2.veo
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2.xco
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2.xise
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2_flist.txt
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2_synth.v
ps2_vga_ver2/ipcore_dir/blk_mem_gen_v7_2_xmdf.tcl
ps2_vga_ver2/ipcore_dir/coregen.cgp
ps2_vga_ver2/ipcore_dir/coregen.log
ps2_vga_ver2/ipcore_dir/create_flappy.tcl
ps2_vga_ver2/ipcore_dir/edit_flappy.tcl
ps2_vga_ver2/ipcore_dir/flappy/
ps2_vga_ver2/ipcore_dir/flappy/blk_mem_gen_v7_2_readme.txt
ps2_vga_ver2/ipcore_dir/flappy/doc/
ps2_vga_ver2/ipcore_dir/flappy/doc/blk_mem_gen_v7_2_vinfo.html
ps2_vga_ver2/ipcore_dir/flappy/doc/pg058-blk-mem-gen.pdf
ps2_vga_ver2/ipcore_dir/flappy/example_design/
ps2_vga_ver2/ipcore_dir/flappy/example_design/flappy_exdes.ucf
ps2_vga_ver2/ipcore_dir/flappy/example_design/flapp

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