Application Note Disclaimer.doc
bldc_ip/bldc_ip_libero_project.prj
bldc_ip/component/
bldc_ip/constraint/
bldc_ip/coreconsole/
bldc_ip/designer/
bldc_ip/designer/impl1/
bldc_ip/designer/impl1/designer.log
bldc_ip/designer/impl1/simulation/
bldc_ip/designer/impl1/top_bldc_ip.adb
bldc_ip/designer/impl1/top_bldc_ip.dtf/
bldc_ip/designer/impl1/top_bldc_ip.dtf/verify.log
bldc_ip/designer/impl1/top_bldc_ip.ide_des
bldc_ip/designer/impl1/top_bldc_ip.stp
bldc_ip/designer/impl1/top_bldc_ip.tcl
bldc_ip/hdl/
bldc_ip/hdl/baud_clk_gen.v
bldc_ip/hdl/bd_bl_speedcontrol.v
bldc_ip/hdl/bdbl_driver.v
bldc_ip/hdl/bldc_ip.v
bldc_ip/hdl/clk_by_2.v
bldc_ip/hdl/clk_gen.v
bldc_ip/hdl/clkdiv_20M_to_10M.v
bldc_ip/hdl/debounce.v
bldc_ip/hdl/debounce_blk.v
bldc_ip/hdl/div_by_16.v
bldc_ip/hdl/divideby5.v
bldc_ip/hdl/global.v
bldc_ip/hdl/mux_hw_sw.v
bldc_ip/hdl/PLL20_to_10.v
bldc_ip/hdl/pwm_gen_bdbl.v
bldc_ip/hdl/recv_control.v
bldc_ip/hdl/serial.v
bldc_ip/hdl/top_bldc.v
bldc_ip/hdl/top_bldc_ip.v
bldc_ip/hdl/top_serial.v
bldc_ip/hdl/xmit_control.v
bldc_ip/phy_synthesis/
bldc_ip/Readme_bldc_ip_project.txt
bldc_ip/simulation/
bldc_ip/simulation/modelsim.ini
bldc_ip/simulation/modelsim.ini.sav
bldc_ip/simulation/modelsim.log
bldc_ip/simulation/presynth/
bldc_ip/simulation/presynth/_info
bldc_ip/simulation/presynth/_temp/
bldc_ip/simulation/presynth/baud_clk_gen/
bldc_ip/simulation/presynth/baud_clk_gen/_primary.dat
bldc_ip/simulation/presynth/baud_clk_gen/_primary.dbs
bldc_ip/simulation/presynth/baud_clk_gen/_primary.vhd
bldc_ip/simulation/presynth/baud_clk_gen/verilog.psm
bldc_ip/simulation/presynth/bd_bl_speedcontrol/
bldc_ip/simulation/presynth/bd_bl_speedcontrol/_primary.dat
bldc_ip/simulation/presynth/bd_bl_speedcontrol/_primary.dbs
bldc_ip/simulation/presynth/bd_bl_speedcontrol/_primary.vhd
bldc_ip/simulation/presynth/bd_bl_speedcontrol/verilog.psm
bldc_ip/simulation/presynth/bdbl_driver/
bldc_ip/simulation/presynth/bdbl_driver/_primary.dat
bldc_ip/simulation/presynth/bdbl_driver/_primary.dbs
bldc_ip/simulation/presynth/bdbl_driver/_primary.vhd
bldc_ip/simulation/presynth/bdbl_driver/verilog.psm
bldc_ip/simulation/presynth/bldc_ip/
bldc_ip/simulation/presynth/bldc_ip/_primary.dat
bldc_ip/simulation/presynth/bldc_ip/_primary.dbs
bldc_ip/simulation/presynth/bldc_ip/_primary.vhd
bldc_ip/simulation/presynth/bldc_ip/verilog.psm
bldc_ip/simulation/presynth/clk_by_2/
bldc_ip/simulation/presynth/clk_by_2/_primary.dat
bldc_ip/simulation/presynth/clk_by_2/_primary.dbs
bldc_ip/simulation/presynth/clk_by_2/_primary.vhd
bldc_ip/simulation/presynth/clk_by_2/verilog.psm
bldc_ip/simulation/presynth/clk_gen/
bldc_ip/simulation/presynth/clk_gen/_primary.dat
bldc_ip/simulation/presynth/clk_gen/_primary.dbs
bldc_ip/simulation/presynth/clk_gen/_primary.vhd
bldc_ip/simulation/presynth/clk_gen/verilog.psm
bldc_ip/simulation/presynth/clkdiv_20@m_to_10@m/
bldc_ip/simulation/presynth/clkdiv_20@m_to_10@m/_primary.dat
bldc_ip/simulation/presynth/clkdiv_20@m_to_10@m/_primary.dbs
bldc_ip/simulation/presynth/clkdiv_20@m_to_10@m/_primary.vhd
bldc_ip/simulation/presynth/clkdiv_20@m_to_10@m/verilog.psm
bldc_ip/simulation/presynth/debounce/
bldc_ip/simulation/presynth/debounce/_primary.dat
bldc_ip/simulation/presynth/debounce/_primary.dbs
bldc_ip/simulation/presynth/debounce/_primary.vhd
bldc_ip/simulation/presynth/debounce/verilog.psm
bldc_ip/simulation/presynth/debounce_blk/
bldc_ip/simulation/presynth/debounce_blk/_primary.dat
bldc_ip/simulation/presynth/debounce_blk/_primary.dbs
bldc_ip/simulation/presynth/debounce_blk/_primary.vhd
bldc_ip/simulation/presynth/debounce_blk/verilog.psm
bldc_ip/simulation/presynth/div_by_16/
bldc_ip/simulation/presynth/div_by_16/_primary.dat
bldc_ip/simulation/presynth/div_by_16/_primary.dbs
bldc_ip/simulation/presynth/div_by_16/_primary.vhd
bldc_ip/simulation/presynth/div_by_16/verilog.psm
bldc_ip/simulation/presynth/divideby5/
bldc_ip/simulation/presynth/divideby5/_primary.dat
bldc_ip/simulation/presynth/divideby5/_primary.dbs
bldc_ip/simulation/presynth/divideby5/_primary.vhd
bldc_ip/simulation/presynth/divideby5/verilog.psm
bldc_ip/simulation/presynth/mux_hw_sw/
bldc_ip/simulation/presynth/mux_hw_sw/_primary.dat
bldc_ip/simulation/presynth/mux_hw_sw/_primary.dbs
bldc_ip/simulation/presynth/mux_hw_sw/_primary.vhd
bldc_ip/simulation/presynth/mux_hw_sw/verilog.psm
bldc_ip/simulation/presynth/pwm_gen_bdbl/
bldc_ip/simulation/presynth/pwm_gen_bdbl/_primary.dat
bldc_ip/simulation/presynth/pwm_gen_bdbl/_primary.dbs
bldc_ip/simulation/presynth/pwm_gen_bdbl/_primary.vhd
bldc_ip/simulation/presynth/pwm_gen_bdbl/verilog.psm
bldc_ip/simulation/presynth/recv_control/
bldc_ip/simulation/presynth/recv_control/_primary.dat
bldc_ip/simulation/presynth/recv_control/_primary.dbs
bldc_ip/simulation/presynth/recv_control/_primary.vhd
bldc_ip/simulation/presynth/recv_control/verilog.psm
bldc_ip/simulation/presynth/serial/
bldc_ip/simulation/presynth/serial/_primary.dat
bldc_ip/simulation/presynth/serial/_primary.dbs
bldc_ip/simulation/presynth/serial/_primary.vhd
bldc_ip/simulation/presynth/serial/verilog.psm
bldc_ip/simulation/presynth/testbench/
bldc_ip/simulation/pre