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文件名称:04_div_clk_1Hz

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2015-11-08
  • 文件大小：
    3.1mb
  • 已下载：
    0次
  • 提 供 者：
    刘***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

verilog HDL 描述分频电路 产生1Hz脉冲方波信号 系统时钟频率50MHz-this is a divide circuit module to get a plus signal of 1Hz
(系统自动生成,下载前可以参看下载内容)

下载文件列表

04_div_clk_1Hz/
04_div_clk_1Hz/quartus/
04_div_clk_1Hz/quartus/db/
04_div_clk_1Hz/quartus/db/.cmp.kpt
04_div_clk_1Hz/quartus/db/div_clk.(0).cnf.cdb
04_div_clk_1Hz/quartus/db/div_clk.(0).cnf.hdb
04_div_clk_1Hz/quartus/db/div_clk.amm.cdb
04_div_clk_1Hz/quartus/db/div_clk.asm.qmsg
04_div_clk_1Hz/quartus/db/div_clk.asm.rdb
04_div_clk_1Hz/quartus/db/div_clk.asm_labs.ddb
04_div_clk_1Hz/quartus/db/div_clk.cbx.xml
04_div_clk_1Hz/quartus/db/div_clk.cmp.bpm
04_div_clk_1Hz/quartus/db/div_clk.cmp.cdb
04_div_clk_1Hz/quartus/db/div_clk.cmp.hdb
04_div_clk_1Hz/quartus/db/div_clk.cmp.kpt
04_div_clk_1Hz/quartus/db/div_clk.cmp.logdb
04_div_clk_1Hz/quartus/db/div_clk.cmp.rdb
04_div_clk_1Hz/quartus/db/div_clk.cmp_merge.kpt
04_div_clk_1Hz/quartus/db/div_clk.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
04_div_clk_1Hz/quartus/db/div_clk.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
04_div_clk_1Hz/quartus/db/div_clk.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
04_div_clk_1Hz/quartus/db/div_clk.db_info
04_div_clk_1Hz/quartus/db/div_clk.eda.qmsg
04_div_clk_1Hz/quartus/db/div_clk.fit.qmsg
04_div_clk_1Hz/quartus/db/div_clk.hier_info
04_div_clk_1Hz/quartus/db/div_clk.hif
04_div_clk_1Hz/quartus/db/div_clk.idb.cdb
04_div_clk_1Hz/quartus/db/div_clk.lpc.html
04_div_clk_1Hz/quartus/db/div_clk.lpc.rdb
04_div_clk_1Hz/quartus/db/div_clk.lpc.txt
04_div_clk_1Hz/quartus/db/div_clk.map.bpm
04_div_clk_1Hz/quartus/db/div_clk.map.cdb
04_div_clk_1Hz/quartus/db/div_clk.map.hdb
04_div_clk_1Hz/quartus/db/div_clk.map.kpt
04_div_clk_1Hz/quartus/db/div_clk.map.logdb
04_div_clk_1Hz/quartus/db/div_clk.map.qmsg
04_div_clk_1Hz/quartus/db/div_clk.map.rdb
04_div_clk_1Hz/quartus/db/div_clk.map_bb.cdb
04_div_clk_1Hz/quartus/db/div_clk.map_bb.hdb
04_div_clk_1Hz/quartus/db/div_clk.map_bb.logdb
04_div_clk_1Hz/quartus/db/div_clk.pre_map.cdb
04_div_clk_1Hz/quartus/db/div_clk.pre_map.hdb
04_div_clk_1Hz/quartus/db/div_clk.root_partition.map.reg_db.cdb
04_div_clk_1Hz/quartus/db/div_clk.routing.rdb
04_div_clk_1Hz/quartus/db/div_clk.rtlv.hdb
04_div_clk_1Hz/quartus/db/div_clk.rtlv_sg.cdb
04_div_clk_1Hz/quartus/db/div_clk.rtlv_sg_swap.cdb
04_div_clk_1Hz/quartus/db/div_clk.sgdiff.cdb
04_div_clk_1Hz/quartus/db/div_clk.sgdiff.hdb
04_div_clk_1Hz/quartus/db/div_clk.sld_design_entry.sci
04_div_clk_1Hz/quartus/db/div_clk.sld_design_entry_dsc.sci
04_div_clk_1Hz/quartus/db/div_clk.smart_action.txt
04_div_clk_1Hz/quartus/db/div_clk.sta.qmsg
04_div_clk_1Hz/quartus/db/div_clk.sta.rdb
04_div_clk_1Hz/quartus/db/div_clk.sta_cmp.8_slow_1200mv_85c.tdb
04_div_clk_1Hz/quartus/db/div_clk.syn_hier_info
04_div_clk_1Hz/quartus/db/div_clk.tis_db_list.ddb
04_div_clk_1Hz/quartus/db/div_clk.tiscmp.fast_1200mv_0c.ddb
04_div_clk_1Hz/quartus/db/div_clk.tiscmp.fastest_slow_1200mv_0c.ddb
04_div_clk_1Hz/quartus/db/div_clk.tiscmp.fastest_slow_1200mv_85c.ddb
04_div_clk_1Hz/quartus/db/div_clk.tiscmp.slow_1200mv_0c.ddb
04_div_clk_1Hz/quartus/db/div_clk.tiscmp.slow_1200mv_85c.ddb
04_div_clk_1Hz/quartus/db/div_clk.tmw_info
04_div_clk_1Hz/quartus/db/logic_util_heursitic.dat
04_div_clk_1Hz/quartus/db/prev_cmp_div_clk.qmsg
04_div_clk_1Hz/quartus/div_clk.asm.rpt
04_div_clk_1Hz/quartus/div_clk.bsf
04_div_clk_1Hz/quartus/div_clk.cdf
04_div_clk_1Hz/quartus/div_clk.done
04_div_clk_1Hz/quartus/div_clk.eda.rpt
04_div_clk_1Hz/quartus/div_clk.fit.rpt
04_div_clk_1Hz/quartus/div_clk.fit.smsg
04_div_clk_1Hz/quartus/div_clk.fit.summary
04_div_clk_1Hz/quartus/div_clk.flow.rpt
04_div_clk_1Hz/quartus/div_clk.jdi
04_div_clk_1Hz/quartus/div_clk.map.rpt
04_div_clk_1Hz/quartus/div_clk.map.summary
04_div_clk_1Hz/quartus/div_clk.pin
04_div_clk_1Hz/quartus/div_clk.pof
04_div_clk_1Hz/quartus/div_clk.qpf
04_div_clk_1Hz/quartus/div_clk.qsf
04_div_clk_1Hz/quartus/div_clk.qws
04_div_clk_1Hz/quartus/div_clk.sld
04_div_clk_1Hz/quartus/div_clk.sof
04_div_clk_1Hz/quartus/div_clk.sta.rpt
04_div_clk_1Hz/quartus/div_clk.sta.summary
04_div_clk_1Hz/quartus/div_clk_assignment_defaults.qdf
04_div_clk_1Hz/quartus/div_clk_nativelink_simulation.rpt
04_div_clk_1Hz/quartus/incremental_db/
04_div_clk_1Hz/quartus/incremental_db/README
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.db_info
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.root_partition.cmp.cdb
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.root_partition.cmp.dfp
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.root_partition.cmp.hdb
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.root_partition.cmp.kpt
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.root_partition.cmp.logdb
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.root_partition.cmp.rcfdb
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.root_partition.map.cdb
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.root_partition.map.dpi
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.root_partition.map.hbdb.cdb
04_div_clk_1Hz/quartus/incremental_db/compiled_partitions/div_clk.root_partition.map.hbdb.hb_info
04_div_c

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