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文件名称:LVDS_SRC

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2015-12-04
  • 文件大小：
    433.57kb
  • 已下载：
    1次
  • 提 供 者：
    王****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

实现LDVS接口数据接收 含有协议结构以及处理-lvds Verilog 512 frame
(系统自动生成,下载前可以参看下载内容)

下载文件列表

LVDS_SRC/
LVDS_SRC/MEMORY_BUFF.v
LVDS_SRC/complete_package.v
LVDS_SRC/decode_module.v
LVDS_SRC/dir/
LVDS_SRC/dir/_xmsgs/
LVDS_SRC/dir/_xmsgs/cg.xmsgs
LVDS_SRC/dir/_xmsgs/pn_parser.xmsgs
LVDS_SRC/dir/coregen.cgp
LVDS_SRC/dir/coregen.log
LVDS_SRC/dir/edit_recv_fifo.tcl
LVDS_SRC/dir/edit_send_fifo.tcl
LVDS_SRC/dir/recv_fifo/
LVDS_SRC/dir/recv_fifo/doc/
LVDS_SRC/dir/recv_fifo/doc/fifo_generator_v9_3_readme.txt
LVDS_SRC/dir/recv_fifo/doc/fifo_generator_v9_3_vinfo.html
LVDS_SRC/dir/recv_fifo/doc/pg057-fifo-generator.pdf
LVDS_SRC/dir/recv_fifo/example_design/
LVDS_SRC/dir/recv_fifo/example_design/recv_fifo_exdes.ucf
LVDS_SRC/dir/recv_fifo/example_design/recv_fifo_exdes.vhd
LVDS_SRC/dir/recv_fifo/fifo_generator_v9_3_readme.txt
LVDS_SRC/dir/recv_fifo/implement/
LVDS_SRC/dir/recv_fifo/implement/implement.bat
LVDS_SRC/dir/recv_fifo/implement/implement.sh
LVDS_SRC/dir/recv_fifo/implement/implement_synplify.bat
LVDS_SRC/dir/recv_fifo/implement/implement_synplify.sh
LVDS_SRC/dir/recv_fifo/implement/planAhead_ise.bat
LVDS_SRC/dir/recv_fifo/implement/planAhead_ise.sh
LVDS_SRC/dir/recv_fifo/implement/planAhead_ise.tcl
LVDS_SRC/dir/recv_fifo/implement/xst.prj
LVDS_SRC/dir/recv_fifo/implement/xst.scr
LVDS_SRC/dir/recv_fifo/simulation/
LVDS_SRC/dir/recv_fifo/simulation/functional/
LVDS_SRC/dir/recv_fifo/simulation/functional/simulate_isim.bat
LVDS_SRC/dir/recv_fifo/simulation/functional/simulate_isim.sh
LVDS_SRC/dir/recv_fifo/simulation/functional/simulate_mti.bat
LVDS_SRC/dir/recv_fifo/simulation/functional/simulate_mti.do
LVDS_SRC/dir/recv_fifo/simulation/functional/simulate_mti.sh
LVDS_SRC/dir/recv_fifo/simulation/functional/simulate_ncsim.bat
LVDS_SRC/dir/recv_fifo/simulation/functional/simulate_vcs.bat
LVDS_SRC/dir/recv_fifo/simulation/functional/ucli_commands.key
LVDS_SRC/dir/recv_fifo/simulation/functional/vcs_session.tcl
LVDS_SRC/dir/recv_fifo/simulation/functional/wave_isim.tcl
LVDS_SRC/dir/recv_fifo/simulation/functional/wave_mti.do
LVDS_SRC/dir/recv_fifo/simulation/functional/wave_ncsim.sv
LVDS_SRC/dir/recv_fifo/simulation/recv_fifo_dgen.vhd
LVDS_SRC/dir/recv_fifo/simulation/recv_fifo_dverif.vhd
LVDS_SRC/dir/recv_fifo/simulation/recv_fifo_pctrl.vhd
LVDS_SRC/dir/recv_fifo/simulation/recv_fifo_pkg.vhd
LVDS_SRC/dir/recv_fifo/simulation/recv_fifo_rng.vhd
LVDS_SRC/dir/recv_fifo/simulation/recv_fifo_synth.vhd
LVDS_SRC/dir/recv_fifo/simulation/recv_fifo_tb.vhd
LVDS_SRC/dir/recv_fifo/simulation/timing/
LVDS_SRC/dir/recv_fifo/simulation/timing/simulate_isim.bat
LVDS_SRC/dir/recv_fifo/simulation/timing/simulate_isim.sh
LVDS_SRC/dir/recv_fifo/simulation/timing/simulate_mti.bat
LVDS_SRC/dir/recv_fifo/simulation/timing/simulate_mti.do
LVDS_SRC/dir/recv_fifo/simulation/timing/simulate_mti.sh
LVDS_SRC/dir/recv_fifo/simulation/timing/simulate_ncsim.bat
LVDS_SRC/dir/recv_fifo/simulation/timing/simulate_vcs.bat
LVDS_SRC/dir/recv_fifo/simulation/timing/ucli_commands.key
LVDS_SRC/dir/recv_fifo/simulation/timing/vcs_session.tcl
LVDS_SRC/dir/recv_fifo/simulation/timing/wave_isim.tcl
LVDS_SRC/dir/recv_fifo/simulation/timing/wave_mti.do
LVDS_SRC/dir/recv_fifo/simulation/timing/wave_ncsim.sv
LVDS_SRC/dir/recv_fifo.asy
LVDS_SRC/dir/recv_fifo.gise
LVDS_SRC/dir/recv_fifo.ncf
LVDS_SRC/dir/recv_fifo.ngc
LVDS_SRC/dir/recv_fifo.sym
LVDS_SRC/dir/recv_fifo.v
LVDS_SRC/dir/recv_fifo.veo
LVDS_SRC/dir/recv_fifo.xco
LVDS_SRC/dir/recv_fifo.xise
LVDS_SRC/dir/recv_fifo_flist.txt
LVDS_SRC/dir/recv_fifo_xmdf.tcl
LVDS_SRC/dir/send_fifo/
LVDS_SRC/dir/send_fifo/doc/
LVDS_SRC/dir/send_fifo/doc/fifo_generator_v9_3_readme.txt
LVDS_SRC/dir/send_fifo/doc/fifo_generator_v9_3_vinfo.html
LVDS_SRC/dir/send_fifo/doc/pg057-fifo-generator.pdf
LVDS_SRC/dir/send_fifo/example_design/
LVDS_SRC/dir/send_fifo/example_design/send_fifo_exdes.ucf
LVDS_SRC/dir/send_fifo/example_design/send_fifo_exdes.vhd
LVDS_SRC/dir/send_fifo/fifo_generator_v9_3_readme.txt
LVDS_SRC/dir/send_fifo/implement/
LVDS_SRC/dir/send_fifo/implement/implement.bat
LVDS_SRC/dir/send_fifo/implement/implement.sh
LVDS_SRC/dir/send_fifo/implement/implement_synplify.bat
LVDS_SRC/dir/send_fifo/implement/implement_synplify.sh
LVDS_SRC/dir/send_fifo/implement/planAhead_ise.bat
LVDS_SRC/dir/send_fifo/implement/planAhead_ise.sh
LVDS_SRC/dir/send_fifo/implement/planAhead_ise.tcl
LVDS_SRC/dir/send_fifo/implement/xst.prj
LVDS_SRC/dir/send_fifo/implement/xst.scr
LVDS_SRC/dir/send_fifo/simulation/
LVDS_SRC/dir/send_fifo/simulation/functional/
LVDS_SRC/dir/send_fifo/simulation/functional/simulate_isim.bat
LVDS_SRC/dir/send_fifo/simulation/functional/simulate_isim.sh
LVDS_SRC/dir/send_fifo/simulation/functional/simulate_mti.bat
LVDS_SRC/dir/send_fifo/simulation/functional/simulate_mti.do
LVDS_SRC/dir/send_fifo/simulation/functional/simulate_mti.sh
LVDS_SRC/dir/send_fifo/simulation/functional/simulate_ncsim.bat
LVDS_SRC/dir/send_fifo/simulation/functional/simulate_vcs.bat
LVDS_SRC/dir/send_fifo/simulation/functional/ucli_commands.key
LVDS_SRC/dir/send_fifo/simulation/functional/vcs_session.tcl
LVDS_SRC/dir/send_fifo/simulation/functional/wave_isim.tcl
LVDS_SRC/dir/send_fifo/simulation/functional/wave_mti.do
LVDS_SRC/dir/send_fifo/simulation/functi

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