文件名称:qnr_verilog
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- 上传时间：2015-12-24
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文件大小：812.77kb
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量化取整QNR内部主要包括一个divider模块及产生数据输出有效和循环结果到最近整数的电路，包含仿真结果图。-Rounding quantization internal QNR includes a divider module and generates data output valid and circulating the results to the nearest integer circuit, including the simulation results shown in Fig.
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下载文件列表
10.4/
10.4/bench_div_top.v
10.4/bench_qnr_top.v
10.4/chart/
10.4/chart/Thumbs.db
10.4/chart/图10-32.bmp
10.4/chart/图10-34.bmp
10.4/chart/图10-35.bmp
10.4/chart/图10-38.bmp
10.4/chart/图10-39.bmp
10.4/chart/表10-4.bmp
10.4/chart/表10-5.bmp
10.4/div_su.v
10.4/div_uu.v
10.4/jpeg_qnr.v
10.4/qnr.cr.mti
10.4/qnr.mpf
10.4/timescale.v
10.4/transcript
10.4/vsim.wlf
10.4/wave/
10.4/wave/Thumbs.db
10.4/wave/bench_qnr_top.bmp
10.4/wave/chk_val.bmp
10.4/wave/div_su.bmp
10.4/wave/div_uu.bmp
10.4/wave/jpeg_qnr.bmp
10.4/work/
10.4/work/_info
10.4/work/bench_div_top/
10.4/work/bench_div_top/_primary.dat
10.4/work/bench_div_top/_primary.vhd
10.4/work/bench_div_top/verilog.asm
10.4/work/bench_qnr_top/
10.4/work/bench_qnr_top/_primary.dat
10.4/work/bench_qnr_top/_primary.vhd
10.4/work/bench_qnr_top/verilog.asm
10.4/work/chk_val/
10.4/work/chk_val/_primary.dat
10.4/work/chk_val/_primary.vhd
10.4/work/chk_val/verilog.asm
10.4/work/div_su/
10.4/work/div_su/_primary.dat
10.4/work/div_su/_primary.vhd
10.4/work/div_su/verilog.asm
10.4/work/div_uu/
10.4/work/div_uu/_primary.dat
10.4/work/div_uu/_primary.vhd
10.4/work/div_uu/verilog.asm
10.4/work/jpeg_qnr/
10.4/work/jpeg_qnr/_primary.dat
10.4/work/jpeg_qnr/_primary.vhd
10.4/work/jpeg_qnr/verilog.asm
10.4/bench_div_top.v
10.4/bench_qnr_top.v
10.4/chart/
10.4/chart/Thumbs.db
10.4/chart/图10-32.bmp
10.4/chart/图10-34.bmp
10.4/chart/图10-35.bmp
10.4/chart/图10-38.bmp
10.4/chart/图10-39.bmp
10.4/chart/表10-4.bmp
10.4/chart/表10-5.bmp
10.4/div_su.v
10.4/div_uu.v
10.4/jpeg_qnr.v
10.4/qnr.cr.mti
10.4/qnr.mpf
10.4/timescale.v
10.4/transcript
10.4/vsim.wlf
10.4/wave/
10.4/wave/Thumbs.db
10.4/wave/bench_qnr_top.bmp
10.4/wave/chk_val.bmp
10.4/wave/div_su.bmp
10.4/wave/div_uu.bmp
10.4/wave/jpeg_qnr.bmp
10.4/work/
10.4/work/_info
10.4/work/bench_div_top/
10.4/work/bench_div_top/_primary.dat
10.4/work/bench_div_top/_primary.vhd
10.4/work/bench_div_top/verilog.asm
10.4/work/bench_qnr_top/
10.4/work/bench_qnr_top/_primary.dat
10.4/work/bench_qnr_top/_primary.vhd
10.4/work/bench_qnr_top/verilog.asm
10.4/work/chk_val/
10.4/work/chk_val/_primary.dat
10.4/work/chk_val/_primary.vhd
10.4/work/chk_val/verilog.asm
10.4/work/div_su/
10.4/work/div_su/_primary.dat
10.4/work/div_su/_primary.vhd
10.4/work/div_su/verilog.asm
10.4/work/div_uu/
10.4/work/div_uu/_primary.dat
10.4/work/div_uu/_primary.vhd
10.4/work/div_uu/verilog.asm
10.4/work/jpeg_qnr/
10.4/work/jpeg_qnr/_primary.dat
10.4/work/jpeg_qnr/_primary.vhd
10.4/work/jpeg_qnr/verilog.asm
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