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文件名称:PS_PLcommunication

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2015-12-26
  • 文件大小：
    22.13mb
  • 已下载：
    0次
  • 提 供 者：
    程**
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

ZYBO开发板的PS与PL通讯简单实例，PL配置switch和led，PS对switch的输入进行处理并赋值给led，点亮相应的灯。-PS and PL communication simple examples ZYBO development board, PL configuration switch and led, PS to switch inputs are processed and assigned to the led, light the corresponding lights.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

project_3/1.tcl
project_3/code.txt
project_3/code2.txt
project_3/code3.txt
project_3/project_3.cache/
project_3/project_3.cache/compile_simlib/
project_3/project_3.cache/compile_simlib/activehdl/
project_3/project_3.cache/compile_simlib/ies/
project_3/project_3.cache/compile_simlib/modelsim/
project_3/project_3.cache/compile_simlib/questa/
project_3/project_3.cache/compile_simlib/riviera/
project_3/project_3.cache/compile_simlib/vcs/
project_3/project_3.cache/wt/
project_3/project_3.cache/wt/java_command_handlers.wdf
project_3/project_3.cache/wt/project.wpc
project_3/project_3.cache/wt/synthesis.wdf
project_3/project_3.cache/wt/synthesis_details.wdf
project_3/project_3.cache/wt/webtalk_pa.xml
project_3/project_3.hw/
project_3/project_3.hw/project_3.lpr
project_3/project_3.ip_user_files/
project_3/project_3.ip_user_files/ipstatic/
project_3/project_3.ip_user_files/ipstatic/processing_system7_bfm_v2_0/
project_3/project_3.ip_user_files/mem_init_files/
project_3/project_3.ip_user_files/mem_init_files/axi_gpio_v2_0_changelog.txt
project_3/project_3.ip_user_files/mem_init_files/axi_protocol_converter_v2_1_changelog.txt
project_3/project_3.ip_user_files/mem_init_files/design_1_bd.tcl
project_3/project_3.ip_user_files/mem_init_files/proc_sys_reset_v5_0_changelog.txt
project_3/project_3.ip_user_files/mem_init_files/processing_system7_v5_5_changelog.txt
project_3/project_3.ip_user_files/mem_init_files/ps7_init.html
project_3/project_3.ip_user_files/mem_init_files/ps7_init.tcl
project_3/project_3.ip_user_files/README.txt
project_3/project_3.ip_user_files/sim_scripts/
project_3/project_3.ip_user_files/sim_scripts/design_1/
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/axi_gpio_v2_0_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/axi_protocol_converter_v2_1_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/compile.do
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/design_1.udo
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/design_1_bd.tcl
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/file_info.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/filelist.f
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/proc_sys_reset_v5_0_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/processing_system7_v5_5_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.html
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.tcl
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/README.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/simulate.do
project_3/project_3.ip_user_files/sim_scripts/design_1/modelsim/wave.do
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/axi_gpio_v2_0_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/axi_protocol_converter_v2_1_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/compile.do
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/design_1.udo
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/design_1_bd.tcl
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/elaborate.do
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/file_info.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/filelist.f
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/proc_sys_reset_v5_0_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/processing_system7_v5_5_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/ps7_init.html
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/ps7_init.tcl
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/README.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/simulate.do
project_3/project_3.ip_user_files/sim_scripts/design_1/questa/wave.do
project_3/project_3.ip_user_files/sim_scripts/design_1/README.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/axi_gpio_v2_0_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/axi_protocol_converter_v2_1_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/design_1_bd.tcl
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/file_info.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/filelist.f
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/proc_sys_reset_v5_0_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/processing_system7_v5_5_changelog.txt
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/ps7_init.html
project_3/project_3.ip_user_files/sim_scripts/design_1/xsim/ps7_init.tcl
project_3/project_3.ip_user_files/sim_

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