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文件名称:fpga-fir

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
  • 上传时间：
    2016-02-17
  • 文件大小：
    1.34mb
  • 已下载：
    0次
  • 提 供 者：
    韩***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog language
(系统自动生成,下载前可以参看下载内容)

下载文件列表

fpga/fpga/db/.cbx.xml
fpga/fpga/db/add_sub_2jh.tdf
fpga/fpga/db/add_sub_3jh.tdf
fpga/fpga/db/add_sub_4jh.tdf
fpga/fpga/db/add_sub_5jh.tdf
fpga/fpga/db/add_sub_6jh.tdf
fpga/fpga/db/add_sub_7jh.tdf
fpga/fpga/db/add_sub_8jh.tdf
fpga/fpga/db/add_sub_98h.tdf
fpga/fpga/db/add_sub_9jh.tdf
fpga/fpga/db/add_sub_ajh.tdf
fpga/fpga/db/add_sub_c8h.tdf
fpga/fpga/db/add_sub_d8h.tdf
fpga/fpga/db/add_sub_e8h.tdf
fpga/fpga/db/add_sub_f8h.tdf
fpga/fpga/db/altsyncram_iqa1.tdf
fpga/fpga/db/FIR_DESIGN.(0).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(0).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(1).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(1).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(10).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(10).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(11).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(11).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(12).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(12).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(13).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(13).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(14).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(14).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(15).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(15).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(16).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(16).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(17).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(17).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(18).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(18).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(19).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(19).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(2).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(2).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(20).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(20).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(21).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(21).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(22).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(22).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(23).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(23).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(24).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(24).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(25).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(25).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(26).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(26).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(27).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(27).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(28).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(28).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(29).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(29).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(3).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(3).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(30).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(30).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(31).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(31).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(32).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(32).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(33).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(33).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(34).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(34).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(35).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(35).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(36).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(36).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(37).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(37).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(38).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(38).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(39).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(39).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(4).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(4).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(40).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(40).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(41).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(41).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(42).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(42).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(43).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(43).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(44).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(44).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(45).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(45).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(46).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(46).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(47).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(47).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(48).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(48).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(49).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(49).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(5).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(5).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(50).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(50).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(51).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(51).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(52).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(52).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(53).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(53).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(54).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(54).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(55).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(55).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(56).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(56).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(57).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(57).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(58).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(58).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(59).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(59).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(6).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(6).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(60).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(60).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(61).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(61).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(62).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(62).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(63).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(63).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(64).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(64).cnf.hdb
fpga/fpga/db/FIR_DESIGN.(7).cnf.cdb
fpga/fpga/db/FIR_DESIGN.(7).cnf.hdb
fpga/fpga/db/

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