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文件名称:FPGA-Connect4-master

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2016-02-24
  • 文件大小：
    1.53mb
  • 已下载：
    0次
  • 提 供 者：
    bol****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Source code for an example VGA controller
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA-Connect4-master/
FPGA-Connect4-master/.gitattributes
FPGA-Connect4-master/.gitignore
FPGA-Connect4-master/Lab4.gise
FPGA-Connect4-master/Lab4.xise
FPGA-Connect4-master/README.md
FPGA-Connect4-master/clock.v
FPGA-Connect4-master/connect4.v
FPGA-Connect4-master/debouncer.v
FPGA-Connect4-master/doc/
FPGA-Connect4-master/doc/Lab 4 Proposal.docx
FPGA-Connect4-master/doc/Lab 4 Report.docx
FPGA-Connect4-master/doc/images/
FPGA-Connect4-master/doc/images/demo.jpg
FPGA-Connect4-master/doc/images/nexys3.jpg
FPGA-Connect4-master/encoder8_3.v
FPGA-Connect4-master/ipcore_dir/
FPGA-Connect4-master/ipcore_dir/Clock.gise
FPGA-Connect4-master/ipcore_dir/Clock.xise
FPGA-Connect4-master/ipcore_dir/Clock50.asy
FPGA-Connect4-master/ipcore_dir/Clock50.gise
FPGA-Connect4-master/ipcore_dir/Clock50.ncf
FPGA-Connect4-master/ipcore_dir/Clock50.sym
FPGA-Connect4-master/ipcore_dir/Clock50.ucf
FPGA-Connect4-master/ipcore_dir/Clock50.v
FPGA-Connect4-master/ipcore_dir/Clock50.veo
FPGA-Connect4-master/ipcore_dir/Clock50.vhd
FPGA-Connect4-master/ipcore_dir/Clock50.vho
FPGA-Connect4-master/ipcore_dir/Clock50.xco
FPGA-Connect4-master/ipcore_dir/Clock50.xdc
FPGA-Connect4-master/ipcore_dir/Clock50.xise
FPGA-Connect4-master/ipcore_dir/Clock50/
FPGA-Connect4-master/ipcore_dir/Clock50/clk_wiz_v3_6_readme.txt
FPGA-Connect4-master/ipcore_dir/Clock50/doc/
FPGA-Connect4-master/ipcore_dir/Clock50/doc/clk_wiz_v3_6_readme.txt
FPGA-Connect4-master/ipcore_dir/Clock50/doc/pg065_clk_wiz.pdf
FPGA-Connect4-master/ipcore_dir/Clock50/example_design/
FPGA-Connect4-master/ipcore_dir/Clock50/example_design/Clock50_exdes.ucf
FPGA-Connect4-master/ipcore_dir/Clock50/example_design/Clock50_exdes.v
FPGA-Connect4-master/ipcore_dir/Clock50/example_design/Clock50_exdes.vhd
FPGA-Connect4-master/ipcore_dir/Clock50/example_design/Clock50_exdes.xdc
FPGA-Connect4-master/ipcore_dir/Clock50/implement/
FPGA-Connect4-master/ipcore_dir/Clock50/implement/implement.bat
FPGA-Connect4-master/ipcore_dir/Clock50/implement/implement.sh
FPGA-Connect4-master/ipcore_dir/Clock50/implement/planAhead_ise.bat
FPGA-Connect4-master/ipcore_dir/Clock50/implement/planAhead_ise.sh
FPGA-Connect4-master/ipcore_dir/Clock50/implement/planAhead_ise.tcl
FPGA-Connect4-master/ipcore_dir/Clock50/implement/planAhead_rdn.bat
FPGA-Connect4-master/ipcore_dir/Clock50/implement/planAhead_rdn.sh
FPGA-Connect4-master/ipcore_dir/Clock50/implement/planAhead_rdn.tcl
FPGA-Connect4-master/ipcore_dir/Clock50/implement/xst.prj
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/Clock50_tb.v
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/Clock50_tb.vhd
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/simcmds.tcl
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/simulate_isim.bat
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/simulate_isim.sh
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/simulate_mti.bat
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/simulate_mti.do
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/simulate_mti.sh
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/simulate_ncsim.sh
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/simulate_vcs.sh
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/ucli_commands.key
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/vcs_session.tcl
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/wave.do
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/functional/wave.sv
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/Clock50_tb.v
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/Clock50_tb.vhd
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/sdf_cmd_file
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/simcmds.tcl
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/simulate_isim.sh
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/simulate_mti.bat
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/simulate_mti.do
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/simulate_mti.sh
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/simulate_ncsim.sh
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/simulate_vcs.sh
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/ucli_commands.key
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/vcs_session.tcl
FPGA-Connect4-master/ipcore_dir/Clock50/simulation/timing/wave.do
FPGA-Connect4-master/ipcore_dir/Clock50_flist.txt
FPGA-Connect4-master/ipcore_dir/Clock50_xmdf.tcl
FPGA-Connect4-master/ipcore_dir/coregen.cgc
FPGA-Connect4-master/ipcore_dir/coregen.cgp
FPGA-Connect4-master/ipcore_dir/edit_Clock50.tcl
FPGA-Connect4-master/ipcore_dir/gen_Clock50.tcl
FPGA-Connect4-master/iseconfig/
FPGA-Connect4-master/iseconfig/Lab4.projectmgr
FPGA-Connect4-master/nexys3.ucf
FPGA-Connect4-master/nexys3.v
FPGA-Connect4-master/nexys3_bitgen.xwbt
FPGA-Connect4-master/

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