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文件名称:vga2

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2016-03-07
  • 文件大小：
    688.95kb
  • 已下载：
    0次
  • 提 供 者：
    l*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

本功能主要实现了VGA的显示，分辨率为1024*768，包内有制作好的coe文件存入rom，适合xilinx芯片-This function is mainly to achieve a VGA display with a resolution of 1024* 768, the bag has produced a good coe file into the rom, for xilinx chip
(系统自动生成,下载前可以参看下载内容)

下载文件列表

vga2/2man.coe
vga2/ceshi.coe
vga2/fft.coe
vga2/fft2.coe
vga2/huahua.coe
vga2/mao.coe
vga2/vga/filter.filter
vga2/vga/ipcore_dir/coregen.cgp
vga2/vga/ipcore_dir/coregen.log
vga2/vga/ipcore_dir/create_pll.tcl
vga2/vga/ipcore_dir/create_rom1.tcl
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/dist_mem_gen_v7_2_readme.txt
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/doc/dist_mem_gen_v7_2_vinfo.html
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/doc/pg063-dist-mem-gen.pdf
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/example_design/dist_mem_gen_v7_2_exdes.ucf
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/example_design/dist_mem_gen_v7_2_exdes.vhd
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/example_design/dist_mem_gen_v7_2_exdes.xdc
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/example_design/dist_mem_gen_v7_2_prod_exdes.vhd
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/implement/implement.bat
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/implement/implement.sh
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/implement/implement_synplify.bat
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/implement/implement_synplify.sh
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/implement/planAhead_ise.bat
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/implement/planAhead_ise.sh
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/implement/planAhead_ise.tcl
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/implement/xst.prj
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/implement/xst.scr
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb.vhd
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_agen.vhd
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_pkg.vhd
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_stim_gen.vhd
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_synth.vhd
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/functional/simulate_mti.bat
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/functional/simulate_mti.do
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/functional/simulate_mti.sh
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/timing/simulate_mti.bat
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/timing/simulate_mti.do
vga2/vga/ipcore_dir/dist_mem_gen_v7_2/simulation/timing/simulate_mti.sh
vga2/vga/ipcore_dir/dist_mem_gen_v7_2.asy
vga2/vga/ipcore_dir/dist_mem_gen_v7_2.gise
vga2/vga/ipcore_dir/dist_mem_gen_v7_2.mif
vga2/vga/ipcore_dir/dist_mem_gen_v7_2.ngc
vga2/vga/ipcore_dir/dist_mem_gen_v7_2.sym
vga2/vga/ipcore_dir/dist_mem_gen_v7_2.v
vga2/vga/ipcore_dir/dist_mem_gen_v7_2.veo
vga2/vga/ipcore_dir/dist_mem_gen_v7_2.xco
vga2/vga/ipcore_dir/dist_mem_gen_v7_2.xise
vga2/vga/ipcore_dir/dist_mem_gen_v7_2_flist.txt
vga2/vga/ipcore_dir/dist_mem_gen_v7_2_xmdf.tcl
vga2/vga/ipcore_dir/edit_rom1.tcl
vga2/vga/ipcore_dir/pll/clk_wiz_v3_6_readme.txt
vga2/vga/ipcore_dir/pll/doc/clk_wiz_v3_6_readme.txt
vga2/vga/ipcore_dir/pll/doc/clk_wiz_v3_6_vinfo.html
vga2/vga/ipcore_dir/pll/doc/pg065_clk_wiz.pdf
vga2/vga/ipcore_dir/pll/example_design/pll_exdes.ucf
vga2/vga/ipcore_dir/pll/example_design/pll_exdes.v
vga2/vga/ipcore_dir/pll/example_design/pll_exdes.xdc
vga2/vga/ipcore_dir/pll/implement/implement.bat
vga2/vga/ipcore_dir/pll/implement/implement.sh
vga2/vga/ipcore_dir/pll/implement/planAhead_ise.bat
vga2/vga/ipcore_dir/pll/implement/planAhead_ise.sh
vga2/vga/ipcore_dir/pll/implement/planAhead_ise.tcl
vga2/vga/ipcore_dir/pll/implement/planAhead_rdn.bat
vga2/vga/ipcore_dir/pll/implement/planAhead_rdn.sh
vga2/vga/ipcore_dir/pll/implement/planAhead_rdn.tcl
vga2/vga/ipcore_dir/pll/implement/xst.prj
vga2/vga/ipcore_dir/pll/implement/xst.scr
vga2/vga/ipcore_dir/pll/simulation/functional/simcmds.tcl
vga2/vga/ipcore_dir/pll/simulation/functional/simulate_isim.bat
vga2/vga/ipcore_dir/pll/simulation/functional/simulate_isim.sh
vga2/vga/ipcore_dir/pll/simulation/functional/simulate_mti.bat
vga2/vga/ipcore_dir/pll/simulation/functional/simulate_mti.do
vga2/vga/ipcore_dir/pll/simulation/functional/simulate_mti.sh
vga2/vga/ipcore_dir/pll/simulation/functional/simulate_ncsim.sh
vga2/vga/ipcore_dir/pll/simulation/functional/simulate_vcs.sh
vga2/vga/ipcore_dir/pll/simulation/functional/ucli_commands.key
vga2/vga/ipcore_dir/pll/simulation/functional/vcs_session.tcl
vga2/vga/ipcore_dir/pll/simulation/functional/wave.do
vga2/vga/ipcore_dir/pll/simulation/functional/wave.sv
vga2/vga/ipcore_dir/pll/simulation/pll_tb.v
vga2/vga/ipcore_dir/pll/simulation/timing/pll_tb.v
vga2/vga/ipcore_dir/pll/simulation/timing/sdf_cmd_file
vga2/vga/ipcore_dir/pll/simulation/timing/simcmds.tcl
vga2/vga/ipcore_dir/pll/simulation/timing/simulate_isim.sh
vga2/vga/ipcore_dir/pll/simulation/timing/simulate_mti.bat
vga2/vga/ipcore_dir/pll/simulation/timing/simulate_mti.do
vga2/vga/ipcore_dir/pll/simulation/timing/simulate_mti.sh
vga2/vga/ipcore_dir/pll/simulation/timing/simulate_ncsim.sh
vga2/vga/ipcore_dir/pll/simulation/timing/simulate_vcs.sh
vga2/vga/ipcore_dir/pll/simulation/timing/ucli_commands.key
vga2/vga/ipcore_dir/pll/simulation/timing/vcs_session.tcl
vga2/vga/ipcore_dir/pll/simulation/timing/wave.do
vga2/vga/ipcore_dir/pll.asy
vga2/vga/ipcore_dir/pll.gise
vga2/vga/ipcore_dir/pll.ncf
vga2/vga/ipcore_dir/pll.sym
vga2/vga/ipc

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