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文件名称:cpu_register_VHDLproject

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2016-05-24
  • 文件大小：
    1.85mb
  • 已下载：
    0次
  • 提 供 者：
    xia****
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，本模块是cpu寄存器组

1.算术逻辑单元（alu_1706）,实现算术逻辑运算

2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。

3.全加器（full_adder）

4.半加器（half_adder）

5.3-8译码器（mutex_3to8）

6.计算机运算器（S6）实现运算器相关功能-VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic

2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).

3. The full adder (full_adder)

4. The half-adder (half_adder)

5.3-8 decoder (mutex_3to8)

6. Computer operator (S6) to achieve operator-related functions
(系统自动生成,下载前可以参看下载内容)

下载文件列表

cpu_register【VHDLproject】/cpu_register.qpf
cpu_register【VHDLproject】/cpu_register.qsf
cpu_register【VHDLproject】/cpu_register.qws
cpu_register【VHDLproject】/cpu_register.vhd
cpu_register【VHDLproject】/cpu_register.vhd.bak
cpu_register【VHDLproject】/db/cpu_register.(0).cnf.cdb
cpu_register【VHDLproject】/db/cpu_register.(0).cnf.hdb
cpu_register【VHDLproject】/db/cpu_register.asm.qmsg
cpu_register【VHDLproject】/db/cpu_register.asm.rdb
cpu_register【VHDLproject】/db/cpu_register.cbx.xml
cpu_register【VHDLproject】/db/cpu_register.cmp.hdb
cpu_register【VHDLproject】/db/cpu_register.cmp.idb
cpu_register【VHDLproject】/db/cpu_register.cmp.kpt
cpu_register【VHDLproject】/db/cpu_register.cmp.rdb
cpu_register【VHDLproject】/db/cpu_register.cmp_merge.kpt
cpu_register【VHDLproject】/db/cpu_register.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
cpu_register【VHDLproject】/db/cpu_register.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
cpu_register【VHDLproject】/db/cpu_register.db_info
cpu_register【VHDLproject】/db/cpu_register.eda.qmsg
cpu_register【VHDLproject】/db/cpu_register.fit.qmsg
cpu_register【VHDLproject】/db/cpu_register.hier_info
cpu_register【VHDLproject】/db/cpu_register.hif
cpu_register【VHDLproject】/db/cpu_register.ipinfo
cpu_register【VHDLproject】/db/cpu_register.lpc.html
cpu_register【VHDLproject】/db/cpu_register.lpc.rdb
cpu_register【VHDLproject】/db/cpu_register.lpc.txt
cpu_register【VHDLproject】/db/cpu_register.map.ammdb
cpu_register【VHDLproject】/db/cpu_register.map.bpm
cpu_register【VHDLproject】/db/cpu_register.map.cdb
cpu_register【VHDLproject】/db/cpu_register.map.hdb
cpu_register【VHDLproject】/db/cpu_register.map.kpt
cpu_register【VHDLproject】/db/cpu_register.map.logdb
cpu_register【VHDLproject】/db/cpu_register.map.qmsg
cpu_register【VHDLproject】/db/cpu_register.map.rdb
cpu_register【VHDLproject】/db/cpu_register.map_bb.cdb
cpu_register【VHDLproject】/db/cpu_register.map_bb.hdb
cpu_register【VHDLproject】/db/cpu_register.map_bb.logdb
cpu_register【VHDLproject】/db/cpu_register.pre_map.hdb
cpu_register【VHDLproject】/db/cpu_register.pti_db_list.ddb
cpu_register【VHDLproject】/db/cpu_register.root_partition.map.reg_db.cdb
cpu_register【VHDLproject】/db/cpu_register.routing.rdb
cpu_register【VHDLproject】/db/cpu_register.rtlv.hdb
cpu_register【VHDLproject】/db/cpu_register.rtlv_sg.cdb
cpu_register【VHDLproject】/db/cpu_register.rtlv_sg_swap.cdb
cpu_register【VHDLproject】/db/cpu_register.sgdiff.cdb
cpu_register【VHDLproject】/db/cpu_register.sgdiff.hdb
cpu_register【VHDLproject】/db/cpu_register.sld_design_entry.sci
cpu_register【VHDLproject】/db/cpu_register.sld_design_entry_dsc.sci
cpu_register【VHDLproject】/db/cpu_register.smart_action.txt
cpu_register【VHDLproject】/db/cpu_register.sta.qmsg
cpu_register【VHDLproject】/db/cpu_register.sta.rdb
cpu_register【VHDLproject】/db/cpu_register.syn_hier_info
cpu_register【VHDLproject】/db/cpu_register.tiscmp.fastest_slow_1200mv_0c.ddb
cpu_register【VHDLproject】/db/cpu_register.tiscmp.fastest_slow_1200mv_85c.ddb
cpu_register【VHDLproject】/db/cpu_register.tiscmp.fast_1200mv_0c.ddb
cpu_register【VHDLproject】/db/cpu_register.tiscmp.slow_1200mv_0c.ddb
cpu_register【VHDLproject】/db/cpu_register.tiscmp.slow_1200mv_85c.ddb
cpu_register【VHDLproject】/db/cpu_register.tis_db_list.ddb
cpu_register【VHDLproject】/db/cpu_register.vpr.ammdb
cpu_register【VHDLproject】/db/logic_util_heursitic.dat
cpu_register【VHDLproject】/db/prev_cmp_cpu_register.qmsg
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.db_info
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.cmp.ammdb
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.cmp.cdb
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.cmp.dfp
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.cmp.hdb
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.cmp.kpt
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.cmp.logdb
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.cmp.rcfdb
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.map.cdb
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.map.dpi
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.map.hbdb.cdb
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.map.hbdb.hb_info
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.map.hbdb.hdb
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.map.hbdb.sig
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.map.hdb
cpu_register【VHDLproject】/incremental_db/compiled_partitions/cpu_register.root_partition.map.kpt
cpu_register【VHDLproject】/incremental_db/README
cpu_register【VHDLproject】/output_files/cpu_register.asm.rpt
cpu_register【VHDLproject】/output_files/cpu_register.done
cpu_register【VHDLproject】/outpu

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