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文件名称:Graphics-and-mixed-VHDL-input

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
  • 上传时间：
    2016-06-01
  • 文件大小：
    163.05kb
  • 已下载：
    0次
  • 提 供 者：
    漆****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

1、　　学习在QUARTUSII软件中模块符号文件的生成与调用。

2、　　掌握模块符号与模块符号之间的连线规则与方法。

3、　　掌握从设计文件到模块符号的创建过程。

-Circuit design, graphics, and mixed VHDL input
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Graphics and mixed VHDL input/example6/exp3.bsf
Graphics and mixed VHDL input/example6/exp3.vhd
Graphics and mixed VHDL input/example6/exp4.bsf
Graphics and mixed VHDL input/example6/exp4.vhd
Graphics and mixed VHDL input/example6/exp5.bsf
Graphics and mixed VHDL input/example6/exp5.vhd
Graphics and mixed VHDL input/example6/exp6.asm.rpt
Graphics and mixed VHDL input/example6/exp6.bdf
Graphics and mixed VHDL input/example6/exp6.done
Graphics and mixed VHDL input/example6/exp6.eda.rpt
Graphics and mixed VHDL input/example6/exp6.fit.eqn
Graphics and mixed VHDL input/example6/exp6.fit.rpt
Graphics and mixed VHDL input/example6/exp6.fit.smsg
Graphics and mixed VHDL input/example6/exp6.fit.summary
Graphics and mixed VHDL input/example6/exp6.flow.rpt
Graphics and mixed VHDL input/example6/exp6.map.eqn
Graphics and mixed VHDL input/example6/exp6.map.rpt
Graphics and mixed VHDL input/example6/exp6.map.summary
Graphics and mixed VHDL input/example6/exp6.pin
Graphics and mixed VHDL input/example6/exp6.pof
Graphics and mixed VHDL input/example6/exp6.qpf
Graphics and mixed VHDL input/example6/exp6.qsf
Graphics and mixed VHDL input/example6/exp6.qws
Graphics and mixed VHDL input/example6/exp6.sof
Graphics and mixed VHDL input/example6/exp6.sta.rpt
Graphics and mixed VHDL input/example6/exp6.sta.summary
Graphics and mixed VHDL input/example6/exp6.tan.rpt
Graphics and mixed VHDL input/example6/exp6.tan.summary
Graphics and mixed VHDL input/example6/exp6_assignment_defaults.qdf
Graphics and mixed VHDL input/example6/incremental_db/compiled_partitions/exp6.root_partition.map.kpt
Graphics and mixed VHDL input/example6/incremental_db/README
Graphics and mixed VHDL input/example6/simulation/modelsim/exp6.sft
Graphics and mixed VHDL input/example6/simulation/modelsim/exp6.vho
Graphics and mixed VHDL input/example6/simulation/modelsim/exp6_8_1200mv_0c_vhd_slow.sdo
Graphics and mixed VHDL input/example6/simulation/modelsim/exp6_8_1200mv_85c_vhd_slow.sdo
Graphics and mixed VHDL input/example6/simulation/modelsim/exp6_min_1200mv_0c_vhd_fast.sdo
Graphics and mixed VHDL input/example6/simulation/modelsim/exp6_modelsim.xrf
Graphics and mixed VHDL input/example6/simulation/modelsim/exp6_vhd.sdo
Graphics and mixed VHDL input/example6/timing/custom/exp6.vho
Graphics and mixed VHDL input/example6/timing/custom/exp6_vhd.sdo
Graphics and mixed VHDL input/example6/timing/primetime/exp6.vho
Graphics and mixed VHDL input/example6/timing/primetime/exp6_pt_vhd.tcl
Graphics and mixed VHDL input/example6/timing/primetime/exp6_vhd.sdo
Graphics and mixed VHDL input/Graphics and mixed VHDL input.docx
Graphics and mixed VHDL input/example6/incremental_db/compiled_partitions
Graphics and mixed VHDL input/example6/simulation/modelsim
Graphics and mixed VHDL input/example6/timing/custom
Graphics and mixed VHDL input/example6/timing/primetime
Graphics and mixed VHDL input/example6/db
Graphics and mixed VHDL input/example6/incremental_db
Graphics and mixed VHDL input/example6/simulation
Graphics and mixed VHDL input/example6/timing
Graphics and mixed VHDL input/example6
Graphics and mixed VHDL input

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