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文件名称:Responder-based-on-VHDL-Design

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
  • 上传时间：
    2016-06-01
  • 文件大小：
    95.06kb
  • 已下载：
    0次
  • 提 供 者：
    漆****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

1、熟悉四人抢答器的工作原理。

2、加深对VHDL语言的理解。

3、掌握EDA开发的基本流程。

-

Responder based on VHDL Design
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Responder based on VHDL Design/example9/exp9.asm.rpt
Responder based on VHDL Design/example9/exp9.done
Responder based on VHDL Design/example9/exp9.eda.rpt
Responder based on VHDL Design/example9/exp9.fit.eqn
Responder based on VHDL Design/example9/exp9.fit.rpt
Responder based on VHDL Design/example9/exp9.fit.smsg
Responder based on VHDL Design/example9/exp9.fit.summary
Responder based on VHDL Design/example9/exp9.flow.rpt
Responder based on VHDL Design/example9/exp9.map.eqn
Responder based on VHDL Design/example9/exp9.map.rpt
Responder based on VHDL Design/example9/exp9.map.summary
Responder based on VHDL Design/example9/exp9.pin
Responder based on VHDL Design/example9/exp9.pof
Responder based on VHDL Design/example9/exp9.qpf
Responder based on VHDL Design/example9/exp9.qsf
Responder based on VHDL Design/example9/exp9.qws
Responder based on VHDL Design/example9/exp9.sof
Responder based on VHDL Design/example9/exp9.sta.rpt
Responder based on VHDL Design/example9/exp9.sta.summary
Responder based on VHDL Design/example9/exp9.tan.rpt
Responder based on VHDL Design/example9/exp9.tan.summary
Responder based on VHDL Design/example9/exp9.vhd
Responder based on VHDL Design/example9/exp9_assignment_defaults.qdf
Responder based on VHDL Design/example9/incremental_db/compiled_partitions/exp9.root_partition.map.kpt
Responder based on VHDL Design/example9/incremental_db/README
Responder based on VHDL Design/example9/simulation/modelsim/exp9.sft
Responder based on VHDL Design/example9/simulation/modelsim/exp9.vho
Responder based on VHDL Design/example9/simulation/modelsim/exp9_8_1200mv_0c_vhd_slow.sdo
Responder based on VHDL Design/example9/simulation/modelsim/exp9_8_1200mv_85c_vhd_slow.sdo
Responder based on VHDL Design/example9/simulation/modelsim/exp9_min_1200mv_0c_vhd_fast.sdo
Responder based on VHDL Design/example9/simulation/modelsim/exp9_modelsim.xrf
Responder based on VHDL Design/example9/simulation/modelsim/exp9_vhd.sdo
Responder based on VHDL Design/example9/timing/custom/exp9.vho
Responder based on VHDL Design/example9/timing/custom/exp9_vhd.sdo
Responder based on VHDL Design/example9/timing/primetime/exp9.vho
Responder based on VHDL Design/example9/timing/primetime/exp9_pt_vhd.tcl
Responder based on VHDL Design/example9/timing/primetime/exp9_vhd.sdo
Responder based on VHDL Design/Responder based on VHDL Design.docx
Responder based on VHDL Design/example9/incremental_db/compiled_partitions
Responder based on VHDL Design/example9/simulation/modelsim
Responder based on VHDL Design/example9/timing/custom
Responder based on VHDL Design/example9/timing/primetime
Responder based on VHDL Design/example9/db
Responder based on VHDL Design/example9/incremental_db
Responder based on VHDL Design/example9/simulation
Responder based on VHDL Design/example9/timing
Responder based on VHDL Design/example9
Responder based on VHDL Design

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