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文件名称:BRAM

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2016-06-13
  • 文件大小：
    3.03mb
  • 已下载：
    0次
  • 提 供 者：
    陈****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

实现先进后出的RAM设计，并在屏幕中显示，用拨码键输入数据，VGA显示read和write和数字-After the realization of the advanced design of the RAM, and displayed on the screen, use the dial keys to enter the code data, VGA display and digital read and write
(系统自动生成,下载前可以参看下载内容)

下载文件列表

BRAM/.lso
BRAM/blk_mem_gen_v7_3.mif
BRAM/Bram.cache/wt/webtalk_pa.xml
BRAM/BRAM.gise
BRAM/Bram.srcs/sources_1/new/frequency.v
BRAM/bram.v
BRAM/BRAM.xise
BRAM/Bram.xpr
BRAM/B_RAM.v
BRAM/clear_shake.prj
BRAM/clear_shake.stx
BRAM/clear_shake.v
BRAM/clear_shake.xst
BRAM/Data_In.prj
BRAM/Data_In.stx
BRAM/Data_In.v
BRAM/Data_In.xst
BRAM/Data_In_isim_beh.exe
BRAM/Data_In_stx_beh.prj
BRAM/divided.prj
BRAM/divided.stx
BRAM/divided.v
BRAM/divided.xst
BRAM/divided_isim_beh.exe
BRAM/divided_stx_beh.prj
BRAM/frequency.prj
BRAM/frequency.stx
BRAM/frequency.v
BRAM/frequency.xst
BRAM/frequency_summary.html
BRAM/fuse.log
BRAM/fuse.xmsgs
BRAM/fuseRelaunch.cmd
BRAM/ipcore_dir/blk_mem_gen_v7_3/blk_mem_gen_v7_3_readme.txt
BRAM/ipcore_dir/blk_mem_gen_v7_3/doc/blk_mem_gen_v7_3_vinfo.html
BRAM/ipcore_dir/blk_mem_gen_v7_3/doc/pg058-blk-mem-gen.pdf
BRAM/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_exdes.ucf
BRAM/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_exdes.vhd
BRAM/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_exdes.xdc
BRAM/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_prod.vhd
BRAM/ipcore_dir/blk_mem_gen_v7_3/implement/implement.bat
BRAM/ipcore_dir/blk_mem_gen_v7_3/implement/implement.sh
BRAM/ipcore_dir/blk_mem_gen_v7_3/implement/planAhead_ise.bat
BRAM/ipcore_dir/blk_mem_gen_v7_3/implement/planAhead_ise.sh
BRAM/ipcore_dir/blk_mem_gen_v7_3/implement/planAhead_ise.tcl
BRAM/ipcore_dir/blk_mem_gen_v7_3/implement/xst.prj
BRAM/ipcore_dir/blk_mem_gen_v7_3/implement/xst.scr
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/addr_gen.vhd
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_synth.vhd
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_tb.vhd
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/bmg_stim_gen.vhd
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/bmg_tb_pkg.vhd
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/simcmds.tcl
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/simulate_isim.bat
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/simulate_mti.bat
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/simulate_mti.do
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/simulate_mti.sh
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/simulate_ncsim.sh
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/simulate_vcs.sh
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/ucli_commands.key
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/vcs_session.tcl
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/wave_mti.do
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/functional/wave_ncsim.sv
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/random.vhd
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/simcmds.tcl
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/simulate_isim.bat
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/simulate_mti.bat
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/simulate_mti.do
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/simulate_mti.sh
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/simulate_ncsim.sh
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/simulate_vcs.sh
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/ucli_commands.key
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/vcs_session.tcl
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/wave_mti.do
BRAM/ipcore_dir/blk_mem_gen_v7_3/simulation/timing/wave_ncsim.sv
BRAM/ipcore_dir/blk_mem_gen_v7_3.asy
BRAM/ipcore_dir/blk_mem_gen_v7_3.gise
BRAM/ipcore_dir/blk_mem_gen_v7_3.mif
BRAM/ipcore_dir/blk_mem_gen_v7_3.ngc
BRAM/ipcore_dir/blk_mem_gen_v7_3.sym
BRAM/ipcore_dir/blk_mem_gen_v7_3.v
BRAM/ipcore_dir/blk_mem_gen_v7_3.veo
BRAM/ipcore_dir/blk_mem_gen_v7_3.xco
BRAM/ipcore_dir/blk_mem_gen_v7_3.xise
BRAM/ipcore_dir/blk_mem_gen_v7_3_flist.txt
BRAM/ipcore_dir/blk_mem_gen_v7_3_xmdf.tcl
BRAM/ipcore_dir/BRAM/blk_mem_gen_v7_3_readme.txt
BRAM/ipcore_dir/BRAM/doc/blk_mem_gen_v7_3_vinfo.html
BRAM/ipcore_dir/BRAM/doc/pg058-blk-mem-gen.pdf
BRAM/ipcore_dir/BRAM/example_design/BRAM_exdes.ucf
BRAM/ipcore_dir/BRAM/example_design/BRAM_exdes.vhd
BRAM/ipcore_dir/BRAM/example_design/BRAM_exdes.xdc
BRAM/ipcore_dir/BRAM/example_design/BRAM_prod.vhd
BRAM/ipcore_dir/BRAM/implement/implement.bat
BRAM/ipcore_dir/BRAM/implement/implement.sh
BRAM/ipcore_dir/BRAM/implement/planAhead_ise.bat
BRAM/ipcore_dir/BRAM/implement/planAhead_ise.sh
BRAM/ipcore_dir/BRAM/implement/planAhead_ise.tcl
BRAM/ipcore_dir/BRAM/implement/xst.prj
BRAM/ipcore_dir/BRAM/implement/xst.scr
BRAM/ipcore_dir/BRAM/simulation/addr_gen.vhd
BRAM/ipcore_dir/BRAM/simulation/bmg_stim_gen.vhd
BRAM/ipcore_dir/BRAM/simulation/bmg_tb_pkg.vhd
BRAM/ipcore_dir/BRAM/simulation/BRAM_synth.vhd
BRAM/ipcore_dir/BRAM/simulation/BRAM_tb.vhd
BRAM/ipcore_dir/BRAM/simulation/checker.vhd
BRAM/ipcore_dir/BRAM/simulation/data_gen.vhd
BRAM/ipcore_dir/BRAM/simulation/functional/simcmds.tcl
BRAM/ipcore_dir/BRAM/simulation/functional/simulate_isim.bat
BRAM/ipcore_dir/BRAM/simulation/functional/simulate_mti.bat
BRAM/ipcore_dir/BRAM/simulation/functional/simulate_mti.do
BRAM/ipcore_dir/BRAM/simulation/functional/simulate_mti.sh
BRAM/ipc

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