文件名称:sdr_ctrl_latest.tar
-
所属分类:
- 标签属性:
- 上传时间:2016-06-23
-
文件大小:2.15mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
SDRAM控制器设计源码,内含仿真代码,测试通过-SDRAM controller design source code, include simulation code, test by
(系统自动生成,下载前可以参看下载内容)
下载文件列表
sdr_ctrl/
sdr_ctrl/tags/
sdr_ctrl/branches/
sdr_ctrl/trunk/
sdr_ctrl/trunk/fpga/
sdr_ctrl/trunk/fpga/actel/
sdr_ctrl/trunk/doc/
sdr_ctrl/trunk/doc/sdram_controller_specs.pdf
sdr_ctrl/trunk/env/
sdr_ctrl/trunk/verif/
sdr_ctrl/trunk/verif/run/
sdr_ctrl/trunk/verif/run/run_all
sdr_ctrl/trunk/verif/run/compile.modelsim
sdr_ctrl/trunk/verif/run/filelist_rtl.f
sdr_ctrl/trunk/verif/run/filelist_top.f
sdr_ctrl/trunk/verif/run/run.do
sdr_ctrl/trunk/verif/run/run_modelsim
sdr_ctrl/trunk/verif/run/read.me
sdr_ctrl/trunk/verif/run/regression_analysis
sdr_ctrl/trunk/verif/run/filelist.f
sdr_ctrl/trunk/verif/run/filelist_core.f
sdr_ctrl/trunk/verif/lib/
sdr_ctrl/trunk/verif/tb/
sdr_ctrl/trunk/verif/tb/tb_core.sv
sdr_ctrl/trunk/verif/tb/tb_top.sv
sdr_ctrl/trunk/verif/log/
sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
sdr_ctrl/trunk/verif/log/core_sdr8_sim.log
sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log
sdr_ctrl/trunk/verif/log/top_SDR_8BIT_complie.log
sdr_ctrl/trunk/verif/log/core_sdr32_sim.log
sdr_ctrl/trunk/verif/log/top_SDR_32BIT_complie.log
sdr_ctrl/trunk/verif/log/top_SDR_16BIT_complie.log
sdr_ctrl/trunk/verif/log/core_SDR_16BIT_complie.log
sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log
sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log
sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log
sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
sdr_ctrl/trunk/verif/dump/
sdr_ctrl/trunk/verif/dump/SDR-16Bit-Write-Transaction.jpg
sdr_ctrl/trunk/verif/dump/SDR-32Bit-Write-Transaction.jpg
sdr_ctrl/trunk/verif/dump/SDR-32Bit-Read-Transaction.jpg
sdr_ctrl/trunk/verif/dump/SDR-16Bit-Read-Transaction.jpg
sdr_ctrl/trunk/verif/dump/Application-ReadRequest.jpg
sdr_ctrl/trunk/verif/dump/Application-WriteRequest.jpg
sdr_ctrl/trunk/verif/agents/
sdr_ctrl/trunk/verif/defs/
sdr_ctrl/trunk/verif/model/
sdr_ctrl/trunk/verif/model/IS42VM16400K.V
sdr_ctrl/trunk/verif/model/mt48lc8m8a2.v
sdr_ctrl/trunk/verif/model/mt48lc2m32b2.v
sdr_ctrl/trunk/verif/model/mt48lc4m32b2.v
sdr_ctrl/trunk/verif/model/mt48lc8m16a2.v
sdr_ctrl/trunk/verif/model/mt48lc4m16.v
sdr_ctrl/trunk/verif/test_case/
sdr_ctrl/trunk/synth/
sdr_ctrl/trunk/synth/constraints/
sdr_ctrl/trunk/synth/constraints/sdrc_top.sdc
sdr_ctrl/trunk/synth/constraints/sdrc_synth.sdc
sdr_ctrl/trunk/rtl/
sdr_ctrl/trunk/rtl/filelist_rtl.f
sdr_ctrl/trunk/rtl/lib/
sdr_ctrl/trunk/rtl/lib/sync_fifo.v
sdr_ctrl/trunk/rtl/lib/async_fifo.v
sdr_ctrl/trunk/rtl/top/
sdr_ctrl/trunk/rtl/top/sdrc_top.v
sdr_ctrl/trunk/rtl/core/
sdr_ctrl/trunk/rtl/core/sdrc_define.v
sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v
sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
sdr_ctrl/trunk/rtl/core/sdrc_core.v
sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
sdr_ctrl/trunk/rtl/wb2sdrc/
sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
sdr_ctrl/trunk/rtl/defs/
sdr_ctrl/trunk/models/
sdr_ctrl/tags/
sdr_ctrl/branches/
sdr_ctrl/trunk/
sdr_ctrl/trunk/fpga/
sdr_ctrl/trunk/fpga/actel/
sdr_ctrl/trunk/doc/
sdr_ctrl/trunk/doc/sdram_controller_specs.pdf
sdr_ctrl/trunk/env/
sdr_ctrl/trunk/verif/
sdr_ctrl/trunk/verif/run/
sdr_ctrl/trunk/verif/run/run_all
sdr_ctrl/trunk/verif/run/compile.modelsim
sdr_ctrl/trunk/verif/run/filelist_rtl.f
sdr_ctrl/trunk/verif/run/filelist_top.f
sdr_ctrl/trunk/verif/run/run.do
sdr_ctrl/trunk/verif/run/run_modelsim
sdr_ctrl/trunk/verif/run/read.me
sdr_ctrl/trunk/verif/run/regression_analysis
sdr_ctrl/trunk/verif/run/filelist.f
sdr_ctrl/trunk/verif/run/filelist_core.f
sdr_ctrl/trunk/verif/lib/
sdr_ctrl/trunk/verif/tb/
sdr_ctrl/trunk/verif/tb/tb_core.sv
sdr_ctrl/trunk/verif/tb/tb_top.sv
sdr_ctrl/trunk/verif/log/
sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
sdr_ctrl/trunk/verif/log/core_sdr8_sim.log
sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log
sdr_ctrl/trunk/verif/log/top_SDR_8BIT_complie.log
sdr_ctrl/trunk/verif/log/core_sdr32_sim.log
sdr_ctrl/trunk/verif/log/top_SDR_32BIT_complie.log
sdr_ctrl/trunk/verif/log/top_SDR_16BIT_complie.log
sdr_ctrl/trunk/verif/log/core_SDR_16BIT_complie.log
sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log
sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log
sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log
sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
sdr_ctrl/trunk/verif/dump/
sdr_ctrl/trunk/verif/dump/SDR-16Bit-Write-Transaction.jpg
sdr_ctrl/trunk/verif/dump/SDR-32Bit-Write-Transaction.jpg
sdr_ctrl/trunk/verif/dump/SDR-32Bit-Read-Transaction.jpg
sdr_ctrl/trunk/verif/dump/SDR-16Bit-Read-Transaction.jpg
sdr_ctrl/trunk/verif/dump/Application-ReadRequest.jpg
sdr_ctrl/trunk/verif/dump/Application-WriteRequest.jpg
sdr_ctrl/trunk/verif/agents/
sdr_ctrl/trunk/verif/defs/
sdr_ctrl/trunk/verif/model/
sdr_ctrl/trunk/verif/model/IS42VM16400K.V
sdr_ctrl/trunk/verif/model/mt48lc8m8a2.v
sdr_ctrl/trunk/verif/model/mt48lc2m32b2.v
sdr_ctrl/trunk/verif/model/mt48lc4m32b2.v
sdr_ctrl/trunk/verif/model/mt48lc8m16a2.v
sdr_ctrl/trunk/verif/model/mt48lc4m16.v
sdr_ctrl/trunk/verif/test_case/
sdr_ctrl/trunk/synth/
sdr_ctrl/trunk/synth/constraints/
sdr_ctrl/trunk/synth/constraints/sdrc_top.sdc
sdr_ctrl/trunk/synth/constraints/sdrc_synth.sdc
sdr_ctrl/trunk/rtl/
sdr_ctrl/trunk/rtl/filelist_rtl.f
sdr_ctrl/trunk/rtl/lib/
sdr_ctrl/trunk/rtl/lib/sync_fifo.v
sdr_ctrl/trunk/rtl/lib/async_fifo.v
sdr_ctrl/trunk/rtl/top/
sdr_ctrl/trunk/rtl/top/sdrc_top.v
sdr_ctrl/trunk/rtl/core/
sdr_ctrl/trunk/rtl/core/sdrc_define.v
sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v
sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
sdr_ctrl/trunk/rtl/core/sdrc_core.v
sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
sdr_ctrl/trunk/rtl/wb2sdrc/
sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
sdr_ctrl/trunk/rtl/defs/
sdr_ctrl/trunk/models/
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.