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文件名称:CD1_PHOTO_ABLUM_1280

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [MacOS] [C/C++] [源码]
  • 上传时间：
    2016-07-13
  • 文件大小：
    2.87mb
  • 已下载：
    0次
  • 提 供 者：
    丁**
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于FPGA的数码像册实验，使用了NIOS做文件系统和JPEG图像解码FPGA和SDRAM做了图像缓存-Based on the FPGA digital image book experiment, using the NIOS to do file system and JPEG image decoding FPGA and SDRAM do the image cache
(系统自动生成,下载前可以参看下载内容)

下载文件列表

CD1_PHOTO_ABLUM_1280/FPGA/.sopc_builder/filters.xml
CD1_PHOTO_ABLUM_1280/FPGA/.sopc_builder/install.ptf
CD1_PHOTO_ABLUM_1280/FPGA/.sopc_builder/install2.ptf
CD1_PHOTO_ABLUM_1280/FPGA/.sopc_builder/preferences.xml
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.asm.rpt
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.cdf
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.done
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.fit.rpt
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.fit.smsg
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.fit.summary
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.flow.rpt
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.jdi
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.map.rpt
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.map.smsg
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.map.summary
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.pin
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.pof
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.qpf
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.qsf
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.sdc
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.sof
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.sta.rpt
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.sta.summary
CD1_PHOTO_ABLUM_1280/FPGA/CD1_PHOTO_ABLUM_1280.v
CD1_PHOTO_ABLUM_1280/FPGA/CONTROL.v
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0.ocp
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0.sdc
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0.v
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_bht_ram.mif
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_dc_tag_ram.mif
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_ic_tag_ram.mif
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_jtag_debug_module_sysclk.v
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_jtag_debug_module_tck.v
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_jtag_debug_module_wrapper.v
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_mult_cell.v
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_ociram_default_contents.mif
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_oci_test_bench.v
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_rf_ram_a.mif
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_rf_ram_b.mif
CD1_PHOTO_ABLUM_1280/FPGA/cpu_0_test_bench.v
CD1_PHOTO_ABLUM_1280/FPGA/epcs_flash_controller_0.v
CD1_PHOTO_ABLUM_1280/FPGA/epcs_flash_controller_0_boot_rom.hex
CD1_PHOTO_ABLUM_1280/FPGA/epcs_flash_controller_0_boot_rom_synth.hex
CD1_PHOTO_ABLUM_1280/FPGA/greybox_tmp/cbx_args.txt
CD1_PHOTO_ABLUM_1280/FPGA/Image_RW_0.v
CD1_PHOTO_ABLUM_1280/FPGA/IP/Image_RW/Image_RW.v
CD1_PHOTO_ABLUM_1280/FPGA/IP/Image_RW/Image_RW_hw.tcl
CD1_PHOTO_ABLUM_1280/FPGA/IP/Image_RW/Image_RW_hw.tcl~
CD1_PHOTO_ABLUM_1280/FPGA/IP/SRAM_16Bit_512K/hdl/SRAM_16Bit_512K.v
CD1_PHOTO_ABLUM_1280/FPGA/IP/SRAM_16Bit_512K/SRAM_16Bit_512K_hw.tcl
CD1_PHOTO_ABLUM_1280/FPGA/jtag_uart_0.v
CD1_PHOTO_ABLUM_1280/FPGA/KEY.v
CD1_PHOTO_ABLUM_1280/FPGA/LED.v
CD1_PHOTO_ABLUM_1280/FPGA/nios.bsf
CD1_PHOTO_ABLUM_1280/FPGA/nios.html
CD1_PHOTO_ABLUM_1280/FPGA/nios.ptf
CD1_PHOTO_ABLUM_1280/FPGA/nios.ptf.8.0
CD1_PHOTO_ABLUM_1280/FPGA/nios.ptf.pre_generation_ptf
CD1_PHOTO_ABLUM_1280/FPGA/nios.qip
CD1_PHOTO_ABLUM_1280/FPGA/nios.sopc
CD1_PHOTO_ABLUM_1280/FPGA/nios.sopcinfo
CD1_PHOTO_ABLUM_1280/FPGA/nios.v
CD1_PHOTO_ABLUM_1280/FPGA/nios_clock_0.v
CD1_PHOTO_ABLUM_1280/FPGA/nios_clock_1.v
CD1_PHOTO_ABLUM_1280/FPGA/nios_generation_script
CD1_PHOTO_ABLUM_1280/FPGA/nios_inst.v
CD1_PHOTO_ABLUM_1280/FPGA/nios_log.txt
CD1_PHOTO_ABLUM_1280/FPGA/nios_sim/atail-f.pl
CD1_PHOTO_ABLUM_1280/FPGA/nios_sim/dummy_file
CD1_PHOTO_ABLUM_1280/FPGA/nios_sim/jtag_uart_0_input_mutex.dat
CD1_PHOTO_ABLUM_1280/FPGA/nios_sim/jtag_uart_0_input_stream.dat
CD1_PHOTO_ABLUM_1280/FPGA/nios_sim/jtag_uart_0_output_stream.dat
CD1_PHOTO_ABLUM_1280/FPGA/PIO.v
CD1_PHOTO_ABLUM_1280/FPGA/PLL108.ppf
CD1_PHOTO_ABLUM_1280/FPGA/PLL108.qip
CD1_PHOTO_ABLUM_1280/FPGA/PLL108.v
CD1_PHOTO_ABLUM_1280/FPGA/PLL50.ppf
CD1_PHOTO_ABLUM_1280/FPGA/PLL50.qip
CD1_PHOTO_ABLUM_1280/FPGA/PLL50.v
CD1_PHOTO_ABLUM_1280/FPGA/PLLJ_PLLSPE_INFO.txt
CD1_PHOTO_ABLUM_1280/FPGA/sdram_0.v
CD1_PHOTO_ABLUM_1280/FPGA/Sdram_FIFO.qip
CD1_PHOTO_ABLUM_1280/FPGA/Sdram_PLL.qip
CD1_PHOTO_ABLUM_1280/FPGA/sopc_add_qip_file.tcl
CD1_PHOTO_ABLUM_1280/FPGA/sopc_builder_log.txt
CD1_PHOTO_ABLUM_1280/FPGA/SPI_CONFIG.v
CD1_PHOTO_ABLUM_1280/FPGA/SPI_MASTER.v
CD1_PHOTO_ABLUM_1280/FPGA/SRAM.v
CD1_PHOTO_ABLUM_1280/FPGA/sram0.v
CD1_PHOTO_ABLUM_1280/FPGA/SRAM_16Bit_512K_0.v
CD1_PHOTO_ABLUM_1280/FPGA/timer_0.v
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Reset_Delay.v
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Sdram_Control_4Port/command.v
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Sdram_Control_4Port/control_interface.v
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_Control_4Port.v
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_FIFO.qip
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_FIFO.v
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_Params.h
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_PLL.ppf
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_PLL.qip
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_PLL.v
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/Sdram_Control_4Port/sdr_data_path.v
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/VGA_Controller.v
CD1_PHOTO_ABLUM_1280/FPGA/USER_CODE/V

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