VGA1_1chuji/
VGA1_1chuji/db/
VGA1_1chuji/db/.cmp.kpt
VGA1_1chuji/db/pll_altpll.v
VGA1_1chuji/db/prev_cmp_vga.qmsg
VGA1_1chuji/db/vga.db_info
VGA1_1chuji/db/vga.ipinfo
VGA1_1chuji/db/vga.sld_design_entry.sci
VGA1_1chuji/db/vga_partition_pins.json
VGA1_1chuji/greybox_tmp/
VGA1_1chuji/greybox_tmp/cbx_args.txt
VGA1_1chuji/incremental_db/
VGA1_1chuji/incremental_db/compiled_partitions/
VGA1_1chuji/incremental_db/compiled_partitions/vga.db_info
VGA1_1chuji/incremental_db/README
VGA1_1chuji/output_files/
VGA1_1chuji/output_files/vga.asm.rpt
VGA1_1chuji/output_files/vga.done
VGA1_1chuji/output_files/vga.eda.rpt
VGA1_1chuji/output_files/vga.fit.rpt
VGA1_1chuji/output_files/vga.fit.smsg
VGA1_1chuji/output_files/vga.fit.summary
VGA1_1chuji/output_files/vga.flow.rpt
VGA1_1chuji/output_files/vga.jdi
VGA1_1chuji/output_files/vga.map.rpt
VGA1_1chuji/output_files/vga.map.summary
VGA1_1chuji/output_files/vga.pin
VGA1_1chuji/output_files/vga.sld
VGA1_1chuji/output_files/vga.sof
VGA1_1chuji/output_files/vga.sta.rpt
VGA1_1chuji/output_files/vga.sta.summary
VGA1_1chuji/pll.ppf
VGA1_1chuji/PLL.qip
VGA1_1chuji/pll.v
VGA1_1chuji/PLLJ_PLLSPE_INFO.txt
VGA1_1chuji/pll_bb.v
VGA1_1chuji/pll_inst.v
VGA1_1chuji/simulation/
VGA1_1chuji/simulation/modelsim/
VGA1_1chuji/simulation/modelsim/modelsim.ini
VGA1_1chuji/simulation/modelsim/msim_transcript
VGA1_1chuji/simulation/modelsim/rtl_work/
VGA1_1chuji/simulation/modelsim/rtl_work/_info
VGA1_1chuji/simulation/modelsim/rtl_work/_lib.qdb
VGA1_1chuji/simulation/modelsim/rtl_work/_lib1_0.qdb
VGA1_1chuji/simulation/modelsim/rtl_work/_lib1_0.qpg
VGA1_1chuji/simulation/modelsim/rtl_work/_lib1_0.qtl
VGA1_1chuji/simulation/modelsim/rtl_work/_vmake
VGA1_1chuji/simulation/modelsim/vga.sft
VGA1_1chuji/simulation/modelsim/vga.vo
VGA1_1chuji/simulation/modelsim/vga_8_1200mv_0c_slow.vo
VGA1_1chuji/simulation/modelsim/vga_8_1200mv_0c_v_slow.sdo
VGA1_1chuji/simulation/modelsim/vga_8_1200mv_85c_slow.vo
VGA1_1chuji/simulation/modelsim/vga_8_1200mv_85c_v_slow.sdo
VGA1_1chuji/simulation/modelsim/vga_min_1200mv_0c_fast.vo
VGA1_1chuji/simulation/modelsim/vga_min_1200mv_0c_v_fast.sdo
VGA1_1chuji/simulation/modelsim/vga_modelsim.xrf
VGA1_1chuji/simulation/modelsim/vga_run_msim_rtl_verilog.do
VGA1_1chuji/simulation/modelsim/vga_run_msim_rtl_verilog.do.bak
VGA1_1chuji/simulation/modelsim/vga_v.sdo
VGA1_1chuji/simulation/modelsim/vsim.wlf
VGA1_1chuji/tb.v
VGA1_1chuji/tb.v.bak
VGA1_1chuji/top.v
VGA1_1chuji/top.v.bak
VGA1_1chuji/vga.qpf
VGA1_1chuji/vga.qsf
VGA1_1chuji/vga.qws
VGA1_1chuji/vga.v
VGA1_1chuji/vga.v.bak
VGA1_1chuji/vga_assignment_defaults.qdf
VGA1_1chuji/vga_nativelink_simulation.rpt