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文件名称:DDR3_128M16bit_2Port64bit

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2016-09-10
  • 文件大小：
    1.48mb
  • 已下载：
    0次
  • 提 供 者：
    艾****
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Xilinx spartan6 DDR3驱动，编程语言Verilog，基于MCB硬核。-Xilinx spartan6 DDR3 driver based on MCB ip core,coding by verilog.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

DDR3_128M16bit_2Port64bit/
DDR3_128M16bit_2Port64bit/chipscope/
DDR3_128M16bit_2Port64bit/chipscope/DDR_calibration.cdc
DDR3_128M16bit_2Port64bit/chipscope/DDR_chipscope.cdc
DDR3_128M16bit_2Port64bit/Ipcore/
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/coregen.cgp
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/coregen.log
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/create_DDR3_MCB_mdl.tcl
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl.gise
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl.ncf
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl.veo
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl.xco
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl.xise
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/docs/
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/docs/ug388.pdf
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/docs/ug416.pdf
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/datasheet.txt
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/log.txt
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/mig.prj
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/create_ise.bat
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/example_top.ucf
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/icon_coregen.xco
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/ila_coregen.xco
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/ise_flow.bat
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/ise_run.txt
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/makeproj.bat
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/mem_interface_top.ut
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/readme.txt
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/rem_files.bat
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/set_ise_prop.tcl
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/par/vio_coregen.xco
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/example_top.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/infrastructure.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/mcb_controller/
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/mcb_controller/iodrp_controller.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/mcb_controller/iodrp_mcb_controller.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/mcb_controller/mcb_raw_wrapper.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/mcb_controller/mcb_soft_calibration.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/mcb_controller/mcb_soft_calibration_top.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/mcb_controller/mcb_ui_top.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/memc_tb_top.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/memc_wrapper.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/afifo.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/cmd_gen.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/cmd_prbs_gen.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/data_prbs_gen.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/init_mem_pattern_ctr.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/mcb_flow_control.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/mcb_traffic_gen.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/rd_data_gen.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/read_data_path.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/read_posted_fifo.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic_gen/sp6_data_gen.v
DDR3_128M16bit_2Port64bit/Ipcore/DDR3_MCB_mdl/DDR3_MCB_mdl/example_design/rtl/traffic

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