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文件名称:fir_vivado

  • 所属分类：
    Windows Develop
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2016-09-18
  • 文件大小：
    59.29mb
  • 已下载：
    1次
  • 提 供 者：
    夏****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

此压缩包里面有基于vivado平台的工程，包括了正弦信号的产生，还有fir滤波器的设计以及fft算法的设计实现-in this package,there are three projects of　

the generation of the signal of sin and the

design of fir filter and the ari
(系统自动生成,下载前可以参看下载内容)

下载文件列表

fir_vivado/
fir_vivado/coe/
fir_vivado/coe/fir_coef_for_coe.coe
fir_vivado/coe/signal_for_coe.coe
fir_vivado/ip/
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/component.xml
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/constraints/
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/constraints/fir_top_ooc.xdc
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/doc/
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/doc/ReleaseNotes.txt
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/hdl/
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/hdl/verilog/
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/hdl/verilog/fir_top.v
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/hdl/verilog/fir_top_mac_muladd_11s_11s_32ns_32_1.v
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/hdl/verilog/fir_top_signal_input_tmp.v
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/hdl/vhdl/
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/hdl/vhdl/fir_top.vhd
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/hdl/vhdl/fir_top_mac_muladd_11s_11s_32ns_32_1.vhd
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/hdl/vhdl/fir_top_signal_input_tmp.vhd
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/misc/
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/misc/logo.png
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/xgui/
fir_vivado/ip/xilinx_com_hls_fir_top_1_0/xgui/fir_top_v1_0.tcl
fir_vivado/project_1/
fir_vivado/project_1/.Xil/
fir_vivado/project_1/ip_upgrade.log
fir_vivado/project_1/project_1.cache/
fir_vivado/project_1/project_1.cache/compile_simlib/
fir_vivado/project_1/project_1.cache/compile_simlib/activehdl/
fir_vivado/project_1/project_1.cache/compile_simlib/ies/
fir_vivado/project_1/project_1.cache/compile_simlib/modelsim/
fir_vivado/project_1/project_1.cache/compile_simlib/questa/
fir_vivado/project_1/project_1.cache/compile_simlib/riviera/
fir_vivado/project_1/project_1.cache/compile_simlib/vcs/
fir_vivado/project_1/project_1.cache/ip/
fir_vivado/project_1/project_1.cache/ip/18f946c7a707cdac/
fir_vivado/project_1/project_1.cache/ip/18f946c7a707cdac/18f946c7a707cdac.xci
fir_vivado/project_1/project_1.cache/ip/18f946c7a707cdac/dbg_hub_CV.dcp
fir_vivado/project_1/project_1.cache/ip/1cda5d1f3030c29d/
fir_vivado/project_1/project_1.cache/ip/1cda5d1f3030c29d/1cda5d1f3030c29d.xci
fir_vivado/project_1/project_1.cache/ip/1cda5d1f3030c29d/u_ila_0_CV.dcp
fir_vivado/project_1/project_1.cache/ip/5a8a90343563d760/
fir_vivado/project_1/project_1.cache/ip/5a8a90343563d760/5a8a90343563d760.xci
fir_vivado/project_1/project_1.cache/ip/5a8a90343563d760/u_ila_0_CV.dcp
fir_vivado/project_1/project_1.cache/ip/61eab77951af087f/
fir_vivado/project_1/project_1.cache/ip/61eab77951af087f/61eab77951af087f.xci
fir_vivado/project_1/project_1.cache/ip/61eab77951af087f/u_ila_0_CV.dcp
fir_vivado/project_1/project_1.cache/ip/a4ad0e26a216f6a9/
fir_vivado/project_1/project_1.cache/ip/a4ad0e26a216f6a9/a4ad0e26a216f6a9.xci
fir_vivado/project_1/project_1.cache/ip/a4ad0e26a216f6a9/u_ila_0_CV.dcp
fir_vivado/project_1/project_1.cache/ip/b18ba793aeb623f1/
fir_vivado/project_1/project_1.cache/ip/b18ba793aeb623f1/b18ba793aeb623f1.xci
fir_vivado/project_1/project_1.cache/ip/b18ba793aeb623f1/u_ila_0_CV.dcp
fir_vivado/project_1/project_1.cache/wt/
fir_vivado/project_1/project_1.cache/wt/java_command_handlers.wdf
fir_vivado/project_1/project_1.cache/wt/project.wpc
fir_vivado/project_1/project_1.cache/wt/synthesis.wdf
fir_vivado/project_1/project_1.cache/wt/synthesis_details.wdf
fir_vivado/project_1/project_1.cache/wt/webtalk_pa.xml
fir_vivado/project_1/project_1.cache/wt/xsim.wdf
fir_vivado/project_1/project_1.hw/
fir_vivado/project_1/project_1.hw/hw_1/
fir_vivado/project_1/project_1.hw/hw_1/hw.xml
fir_vivado/project_1/project_1.hw/hw_1/layout/
fir_vivado/project_1/project_1.hw/hw_1/layout/hw_ila_1.layout
fir_vivado/project_1/project_1.hw/hw_1/wave/
fir_vivado/project_1/project_1.hw/hw_1/wave/hw_ila_data_1/
fir_vivado/project_1/project_1.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wcfg
fir_vivado/project_1/project_1.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb
fir_vivado/project_1/project_1.hw/project_1.lpr
fir_vivado/project_1/project_1.ip_user_files/
fir_vivado/project_1/project_1.ip_user_files/README.txt
fir_vivado/project_1/project_1.ip_user_files/bd/
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/hdl/
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/hdl/design_1.v
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/ip/
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_blk_mem_gen_0_0/
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_blk_mem_gen_0_0/sim/
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_blk_mem_gen_0_0/sim/design_1_blk_mem_gen_0_0.v
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_blk_mem_gen_1_0/
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_blk_mem_gen_1_0/sim/
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_blk_mem_gen_1_0/sim/design_1_blk_mem_gen_1_0.v
fir_vivado/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_blk_mem_gen_2_1/
fir_vivado/project_1/project_1.ip_us

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