gpio-master/
gpio-master/bench/
gpio-master/bench/verilog/
gpio-master/bench/verilog/clkrst.v
gpio-master/bench/verilog/gpio_mon.v
gpio-master/bench/verilog/gpio_testbench.v
gpio-master/bench/verilog/tb_defines.v
gpio-master/bench/verilog/tb_tasks.v
gpio-master/bench/verilog/timescale.v
gpio-master/bench/verilog/wb_master.v
gpio-master/doc/
gpio-master/doc/gpio_spec.pdf
gpio-master/doc/src/
gpio-master/doc/src/gpio_spec.doc
gpio-master/rtl/
gpio-master/rtl/verilog/
gpio-master/rtl/verilog/gpio_defines.v
gpio-master/rtl/verilog/gpio_top.v
gpio-master/sim/
gpio-master/sim/rtl_sim/
gpio-master/sim/rtl_sim/bin/
gpio-master/sim/rtl_sim/bin/INCA_libs/
gpio-master/sim/rtl_sim/bin/INCA_libs/worklib/
gpio-master/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
gpio-master/sim/rtl_sim/bin/cds.lib
gpio-master/sim/rtl_sim/bin/hdl.var
gpio-master/sim/rtl_sim/bin/rtl_file_list
gpio-master/sim/rtl_sim/bin/sim.sh
gpio-master/sim/rtl_sim/bin/sim_file_list
gpio-master/sim/rtl_sim/log/
gpio-master/sim/rtl_sim/log/ncelab.log
gpio-master/sim/rtl_sim/log/ncsim.log
gpio-master/sim/rtl_sim/log/ncvlog.log
gpio-master/sim/rtl_sim/run/
gpio-master/sim/rtl_sim/run/ncelab.args
gpio-master/sim/rtl_sim/run/ncsim.args
gpio-master/sim/rtl_sim/run/ncsim.tcl
gpio-master/sim/rtl_sim/run/ncvlog.args
gpio-master/sim/rtl_sim/run/run_sim
gpio-master/sim/rtl_sim/run/run_sim_gpio
gpio-master/syn/
gpio-master/syn/bin/
gpio-master/syn/bin/cons_art_umc18.inc
gpio-master/syn/bin/cons_vs_umc18.inc
gpio-master/syn/bin/read_design.inc
gpio-master/syn/bin/reports.inc
gpio-master/syn/bin/save_design.inc
gpio-master/syn/bin/select_tech.inc
gpio-master/syn/bin/set_env.inc
gpio-master/syn/bin/tech_art_umc18.inc
gpio-master/syn/bin/tech_vs_umc18.inc
gpio-master/syn/bin/top_gpio.scr
gpio-master/syn/run/
gpio-master/syn/run/dodesign