rd1142_spi_slave_controller/rd1142/
rd1142_spi_slave_controller/rd1142/docs/
rd1142_spi_slave_controller/rd1142/docs/~$revision_history.xlsx
rd1142_spi_slave_controller/rd1142/docs/rd1142.pdf
rd1142_spi_slave_controller/rd1142/docs/rd1142_readme.txt
rd1142_spi_slave_controller/rd1142/project/
rd1142_spi_slave_controller/rd1142/project/iCE40/
rd1142_spi_slave_controller/rd1142/project/iCE40/vhdl/
rd1142_spi_slave_controller/rd1142/project/iCE40/vhdl/iCE40_vhdl/
rd1142_spi_slave_controller/rd1142/project/iCE40/vhdl/iCE40_vhdl/iCE40_vhdl_sbt.project
rd1142_spi_slave_controller/rd1142/project/iCE40/vhdl/iCE40_vhdl/iCE40_vhdl_syn.prj
rd1142_spi_slave_controller/rd1142/simulation/
rd1142_spi_slave_controller/rd1142/simulation/iCE40/
rd1142_spi_slave_controller/rd1142/simulation/iCE40/vhdl/
rd1142_spi_slave_controller/rd1142/simulation/iCE40/vhdl/rtl_vhdl.do
rd1142_spi_slave_controller/rd1142/simulation/iCE40/vhdl/timing_vhdl.do
rd1142_spi_slave_controller/rd1142/source/
rd1142_spi_slave_controller/rd1142/source/verilog/
rd1142_spi_slave_controller/rd1142/source/verilog/spi_slave_top.v
rd1142_spi_slave_controller/rd1142/source/vhdl/
rd1142_spi_slave_controller/rd1142/source/vhdl/spi_slave.vhd
rd1142_spi_slave_controller/rd1142/testbench/
rd1142_spi_slave_controller/rd1142/testbench/vhdl/
rd1142_spi_slave_controller/rd1142/testbench/vhdl/spi_slave_tb.vhd