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文件名称:pcpu_handle_mem

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  • 上传时间:
    2016-10-27
  • 文件大小:
    10.86mb
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介绍说明--下载内容来自于网络,使用问题请自行百度

Verilog实现五级流水线CPU,hazard以及时序功能已经实现。-Realize five-stage pipeline CPU
(系统自动生成,下载前可以参看下载内容)

下载文件列表

pcpu_handle_mem/clk_div.v
pcpu_handle_mem/clk_div_isim_beh.exe
pcpu_handle_mem/cpu.bgn
pcpu_handle_mem/cpu.bit
pcpu_handle_mem/cpu.bld
pcpu_handle_mem/cpu.cmd_log
pcpu_handle_mem/cpu.drc
pcpu_handle_mem/cpu.lso
pcpu_handle_mem/cpu.ncd
pcpu_handle_mem/cpu.ngc
pcpu_handle_mem/cpu.ngd
pcpu_handle_mem/cpu.ngr
pcpu_handle_mem/cpu.pad
pcpu_handle_mem/cpu.par
pcpu_handle_mem/cpu.pcf
pcpu_handle_mem/cpu.prj
pcpu_handle_mem/cpu.ptwx
pcpu_handle_mem/cpu.stx
pcpu_handle_mem/cpu.syr
pcpu_handle_mem/cpu.twr
pcpu_handle_mem/cpu.twx
pcpu_handle_mem/cpu.unroutes
pcpu_handle_mem/cpu.ut
pcpu_handle_mem/cpu.v
pcpu_handle_mem/cpu.xpi
pcpu_handle_mem/cpu.xst
pcpu_handle_mem/cpu_bitgen.xwbt
pcpu_handle_mem/cpu_envsettings.html
pcpu_handle_mem/cpu_guide.ncd
pcpu_handle_mem/cpu_icf.ucf
pcpu_handle_mem/cpu_isim_beh.exe
pcpu_handle_mem/cpu_map.map
pcpu_handle_mem/cpu_map.mrp
pcpu_handle_mem/cpu_map.ncd
pcpu_handle_mem/cpu_map.ngm
pcpu_handle_mem/cpu_map.xrpt
pcpu_handle_mem/cpu_ngdbuild.xrpt
pcpu_handle_mem/cpu_pad.csv
pcpu_handle_mem/cpu_pad.txt
pcpu_handle_mem/cpu_par.xrpt
pcpu_handle_mem/cpu_summary.html
pcpu_handle_mem/cpu_summary.xml
pcpu_handle_mem/cpu_tb.v
pcpu_handle_mem/cpu_tb2.v
pcpu_handle_mem/cpu_tb2_beh.prj
pcpu_handle_mem/cpu_tb2_isim_beh.exe
pcpu_handle_mem/cpu_tb2_isim_beh.wdb
pcpu_handle_mem/cpu_tb_beh.prj
pcpu_handle_mem/cpu_tb_isim_beh.exe
pcpu_handle_mem/cpu_tb_isim_beh.wdb
pcpu_handle_mem/cpu_tb_stx_beh.prj
pcpu_handle_mem/cpu_usage.xml
pcpu_handle_mem/cpu_xst.xrpt
pcpu_handle_mem/data_cache.v
pcpu_handle_mem/data_cache_isim_beh.exe
pcpu_handle_mem/data_mem.v
pcpu_handle_mem/data_mem_isim_beh.exe
pcpu_handle_mem/d_mem.mif
pcpu_handle_mem/d_mem.v
pcpu_handle_mem/fuse.log
pcpu_handle_mem/fuse.xmsgs
pcpu_handle_mem/fuseRelaunch.cmd
pcpu_handle_mem/inst_mem.v
pcpu_handle_mem/inst_mem_isim_beh.exe
pcpu_handle_mem/inst_mem_isim_beh1.wdb
pcpu_handle_mem/ipcore_dir/coregen.cgp
pcpu_handle_mem/ipcore_dir/coregen.log
pcpu_handle_mem/ipcore_dir/create_d_mem.tcl
pcpu_handle_mem/ipcore_dir/create_i_mem.tcl
pcpu_handle_mem/ipcore_dir/d_mem/blk_mem_gen_v7_3_readme.txt
pcpu_handle_mem/ipcore_dir/d_mem/doc/blk_mem_gen_v7_3_vinfo.html
pcpu_handle_mem/ipcore_dir/d_mem/doc/pg058-blk-mem-gen.pdf
pcpu_handle_mem/ipcore_dir/d_mem/example_design/d_mem_exdes.ucf
pcpu_handle_mem/ipcore_dir/d_mem/example_design/d_mem_exdes.vhd
pcpu_handle_mem/ipcore_dir/d_mem/example_design/d_mem_exdes.xdc
pcpu_handle_mem/ipcore_dir/d_mem/example_design/d_mem_prod.vhd
pcpu_handle_mem/ipcore_dir/d_mem/implement/implement.bat
pcpu_handle_mem/ipcore_dir/d_mem/implement/implement.sh
pcpu_handle_mem/ipcore_dir/d_mem/implement/planAhead_ise.bat
pcpu_handle_mem/ipcore_dir/d_mem/implement/planAhead_ise.sh
pcpu_handle_mem/ipcore_dir/d_mem/implement/planAhead_ise.tcl
pcpu_handle_mem/ipcore_dir/d_mem/implement/xst.prj
pcpu_handle_mem/ipcore_dir/d_mem/implement/xst.scr
pcpu_handle_mem/ipcore_dir/d_mem/simulation/addr_gen.vhd
pcpu_handle_mem/ipcore_dir/d_mem/simulation/bmg_stim_gen.vhd
pcpu_handle_mem/ipcore_dir/d_mem/simulation/bmg_tb_pkg.vhd
pcpu_handle_mem/ipcore_dir/d_mem/simulation/checker.vhd
pcpu_handle_mem/ipcore_dir/d_mem/simulation/data_gen.vhd
pcpu_handle_mem/ipcore_dir/d_mem/simulation/d_mem_synth.vhd
pcpu_handle_mem/ipcore_dir/d_mem/simulation/d_mem_tb.vhd
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/simcmds.tcl
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/simulate_isim.bat
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/simulate_mti.bat
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/simulate_mti.do
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/simulate_mti.sh
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/simulate_ncsim.sh
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/simulate_vcs.sh
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/ucli_commands.key
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/vcs_session.tcl
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/wave_mti.do
pcpu_handle_mem/ipcore_dir/d_mem/simulation/functional/wave_ncsim.sv
pcpu_handle_mem/ipcore_dir/d_mem/simulation/random.vhd
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/simcmds.tcl
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/simulate_isim.bat
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/simulate_mti.bat
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/simulate_mti.do
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/simulate_mti.sh
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/simulate_ncsim.sh
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/simulate_vcs.sh
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/ucli_commands.key
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/vcs_session.tcl
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/wave_mti.do
pcpu_handle_mem/ipcore_dir/d_mem/simulation/timing/wave_ncsim.sv
pcpu_handle_mem/ipcore_dir/d_mem.asy
pcpu_handle_mem/ipcore_dir/d_mem.gise
pcpu_handle_mem/ipcore_dir/d_mem.mif
pcpu_handle_mem/ipcore_dir/d_mem.ncf
pcpu_handle_mem/ipcore_dir/d_mem.ngc
pcpu_handle_mem/ipcore_dir/d_mem.sym
pcpu_handle_mem/ipcore_dir/d_mem.v
pcpu_handle_mem/ipcore_dir/

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