文件名称:BCH
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implemention the BCH coding in VHDL: THE DESIGN OF A VHDL BASED SYNTHESIS TOOL FOR BCH CODECS
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下载文件列表
BCH/bch_thesis/APPEND.DOC
BCH/bch_thesis/BEGIN.DOC
BCH/bch_thesis/Ch1.doc
BCH/bch_thesis/Ch2.doc
BCH/bch_thesis/Ch3.doc
BCH/bch_thesis/Ch4.doc
BCH/bch_thesis/Ch5.doc
BCH/bch_thesis/REFER.DOC
BCH/bch_thesis/~$APPEND.DOC
BCH/bch_thesis/~$Ch2.doc
BCH/bch_thesis/~$Ch3.doc
BCH/bch_thesis/~$Ch4.doc
BCH/examples/BCH15_11/CONST.VHD
BCH/examples/BCH15_11/DBUF.RPT
BCH/examples/BCH15_11/DCH1.RPT
BCH/examples/BCH15_11/DCOUNT.RPT
BCH/examples/BCH15_11/DEC.RPT
BCH/examples/BCH15_11/DEC.VHD
BCH/examples/BCH15_11/DSYN1.RPT
BCH/examples/BCH15_11/ECOUNT.RPT
BCH/examples/BCH15_11/ENC.RPT
BCH/examples/BCH15_11/ENC.VHD
BCH/examples/BCH15_11/ERING.RPT
BCH/examples/BCH15_11/SIM.CMD
BCH/examples/BCH15_11/SIM.CME
BCH/examples/BCH15_11/SIM.VHD
BCH/examples/Bch15_5/chian block.txt
BCH/examples/Bch15_5/CONST.VHD
BCH/examples/Bch15_5/DEC.VHD
BCH/examples/Bch15_5/ENC.VHD
BCH/examples/Bch15_5/new 3.txt
BCH/examples/Bch15_5/SIM.TXT
BCH/examples/Bch15_5/SIM.VHD
BCH/examples/Bch15_7/CONST.VHD
BCH/examples/Bch15_7/DEC.VHD
BCH/examples/Bch15_7/ENC.VHD
BCH/examples/Bch15_7/new 9.txt
BCH/examples/Bch15_7/SIM.CMD
BCH/examples/Bch15_7/SIM.TXT
BCH/examples/Bch15_7/SIM.VHD
BCH/examples/UART/uart (2).vhd
BCH/examples/UART/uart.vhd
BCH/examples/UART/uarttest.vhd
BCH/proj/B.txt
BCH/proj/bch.c
BCH/proj/bch.exe
BCH/proj/Bch.in
BCH/proj/BCH.VHT
BCH/proj/BCH1.VHT
BCH/proj/BCH2.VHT
BCH/proj/BCH3.VHT
BCH/proj/BCHIO.VHD
BCH/proj/BCHS.VHT
BCH/proj/calcolate_syn.txt
BCH/proj/chsim.txt
BCH/proj/const.vhd
BCH/proj/dec.vhd
BCH/proj/DECH.txt
BCH/proj/enc.vhd
BCH/proj/input.txt
BCH/proj/lat.txt
BCH/proj/lat1.txt
BCH/proj/new 2.txt
BCH/proj/new 3.txt
BCH/proj/new .txt
BCH/proj/root.txt
BCH/proj/rootr.txt
BCH/proj/sfim.txt
BCH/proj/sim.txt
BCH/proj/sim.vhd
BCH/proj/syn1.txt
BCH/proj/Syn3.txt
BCH/proj/Syn5.txt
BCH/examples/BCH15_11
BCH/examples/Bch15_5
BCH/examples/Bch15_7
BCH/examples/UART
BCH/bch_thesis
BCH/examples
BCH/proj
BCH
BCH/bch_thesis/BEGIN.DOC
BCH/bch_thesis/Ch1.doc
BCH/bch_thesis/Ch2.doc
BCH/bch_thesis/Ch3.doc
BCH/bch_thesis/Ch4.doc
BCH/bch_thesis/Ch5.doc
BCH/bch_thesis/REFER.DOC
BCH/bch_thesis/~$APPEND.DOC
BCH/bch_thesis/~$Ch2.doc
BCH/bch_thesis/~$Ch3.doc
BCH/bch_thesis/~$Ch4.doc
BCH/examples/BCH15_11/CONST.VHD
BCH/examples/BCH15_11/DBUF.RPT
BCH/examples/BCH15_11/DCH1.RPT
BCH/examples/BCH15_11/DCOUNT.RPT
BCH/examples/BCH15_11/DEC.RPT
BCH/examples/BCH15_11/DEC.VHD
BCH/examples/BCH15_11/DSYN1.RPT
BCH/examples/BCH15_11/ECOUNT.RPT
BCH/examples/BCH15_11/ENC.RPT
BCH/examples/BCH15_11/ENC.VHD
BCH/examples/BCH15_11/ERING.RPT
BCH/examples/BCH15_11/SIM.CMD
BCH/examples/BCH15_11/SIM.CME
BCH/examples/BCH15_11/SIM.VHD
BCH/examples/Bch15_5/chian block.txt
BCH/examples/Bch15_5/CONST.VHD
BCH/examples/Bch15_5/DEC.VHD
BCH/examples/Bch15_5/ENC.VHD
BCH/examples/Bch15_5/new 3.txt
BCH/examples/Bch15_5/SIM.TXT
BCH/examples/Bch15_5/SIM.VHD
BCH/examples/Bch15_7/CONST.VHD
BCH/examples/Bch15_7/DEC.VHD
BCH/examples/Bch15_7/ENC.VHD
BCH/examples/Bch15_7/new 9.txt
BCH/examples/Bch15_7/SIM.CMD
BCH/examples/Bch15_7/SIM.TXT
BCH/examples/Bch15_7/SIM.VHD
BCH/examples/UART/uart (2).vhd
BCH/examples/UART/uart.vhd
BCH/examples/UART/uarttest.vhd
BCH/proj/B.txt
BCH/proj/bch.c
BCH/proj/bch.exe
BCH/proj/Bch.in
BCH/proj/BCH.VHT
BCH/proj/BCH1.VHT
BCH/proj/BCH2.VHT
BCH/proj/BCH3.VHT
BCH/proj/BCHIO.VHD
BCH/proj/BCHS.VHT
BCH/proj/calcolate_syn.txt
BCH/proj/chsim.txt
BCH/proj/const.vhd
BCH/proj/dec.vhd
BCH/proj/DECH.txt
BCH/proj/enc.vhd
BCH/proj/input.txt
BCH/proj/lat.txt
BCH/proj/lat1.txt
BCH/proj/new 2.txt
BCH/proj/new 3.txt
BCH/proj/new .txt
BCH/proj/root.txt
BCH/proj/rootr.txt
BCH/proj/sfim.txt
BCH/proj/sim.txt
BCH/proj/sim.vhd
BCH/proj/syn1.txt
BCH/proj/Syn3.txt
BCH/proj/Syn5.txt
BCH/examples/BCH15_11
BCH/examples/Bch15_5
BCH/examples/Bch15_7
BCH/examples/UART
BCH/bch_thesis
BCH/examples
BCH/proj
BCH
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