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文件名称:DDR2_Control

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2017-02-16
  • 文件大小：
    12.44mb
  • 已下载：
    0次
  • 提 供 者：
    冯****
  • 相关连接：
    无
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修正介绍说明

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本源码是用FPGA控制DDR2芯片的vhdl源码，并使用了modelsim仿真软件测试代码-The source is the use of FPGA control DDR2 chip vhdl source, and the use of modelsim simulation software test code
(系统自动生成,下载前可以参看下载内容)

下载文件列表

DDR2_Control/
DDR2_Control/Chipscope/
DDR2_Control/Chipscope/siga-s16.cpj
DDR2_Control/Siga_DDR2_MIG_Design.cgc
DDR2_Control/Siga_DDR2_MIG_Design.cgp
DDR2_Control/_xmsgs/
DDR2_Control/_xmsgs/pn_parser.xmsgs
DDR2_Control/iseconfig/
DDR2_Control/iseconfig/mig_37.projectmgr
DDR2_Control/iseconfig/mig_37.xreport
DDR2_Control/mig_37/
DDR2_Control/mig_37/docs/
DDR2_Control/mig_37/docs/ug388.pdf
DDR2_Control/mig_37/docs/ug416.pdf
DDR2_Control/mig_37/example_design/
DDR2_Control/mig_37/example_design/datasheet.txt
DDR2_Control/mig_37/example_design/log.txt
DDR2_Control/mig_37/example_design/mig.prj
DDR2_Control/mig_37/example_design/par/
DDR2_Control/mig_37/example_design/par/_ngo/
DDR2_Control/mig_37/example_design/par/_ngo/netlist.lst
DDR2_Control/mig_37/example_design/par/_xmsgs/
DDR2_Control/mig_37/example_design/par/_xmsgs/bitgen.xmsgs
DDR2_Control/mig_37/example_design/par/_xmsgs/map.xmsgs
DDR2_Control/mig_37/example_design/par/_xmsgs/ngdbuild.xmsgs
DDR2_Control/mig_37/example_design/par/_xmsgs/par.xmsgs
DDR2_Control/mig_37/example_design/par/_xmsgs/pn_parser.xmsgs
DDR2_Control/mig_37/example_design/par/_xmsgs/trce.xmsgs
DDR2_Control/mig_37/example_design/par/_xmsgs/xst.xmsgs
DDR2_Control/mig_37/example_design/par/coregen.cgc
DDR2_Control/mig_37/example_design/par/coregen.cgp
DDR2_Control/mig_37/example_design/par/coregen.log
DDR2_Control/mig_37/example_design/par/create_ise.bat
DDR2_Control/mig_37/example_design/par/example_top.bgn
DDR2_Control/mig_37/example_design/par/example_top.bit
DDR2_Control/mig_37/example_design/par/example_top.bld
DDR2_Control/mig_37/example_design/par/example_top.cdc
DDR2_Control/mig_37/example_design/par/example_top.cmd_log
DDR2_Control/mig_37/example_design/par/example_top.drc
DDR2_Control/mig_37/example_design/par/example_top.ncd
DDR2_Control/mig_37/example_design/par/example_top.ngc
DDR2_Control/mig_37/example_design/par/example_top.ngd
DDR2_Control/mig_37/example_design/par/example_top.ngr
DDR2_Control/mig_37/example_design/par/example_top.pad
DDR2_Control/mig_37/example_design/par/example_top.par
DDR2_Control/mig_37/example_design/par/example_top.pcf
DDR2_Control/mig_37/example_design/par/example_top.prj
DDR2_Control/mig_37/example_design/par/example_top.ptwx
DDR2_Control/mig_37/example_design/par/example_top.stx
DDR2_Control/mig_37/example_design/par/example_top.syr
DDR2_Control/mig_37/example_design/par/example_top.twr
DDR2_Control/mig_37/example_design/par/example_top.twx
DDR2_Control/mig_37/example_design/par/example_top.ucf
DDR2_Control/mig_37/example_design/par/example_top.unroutes
DDR2_Control/mig_37/example_design/par/example_top.ut
DDR2_Control/mig_37/example_design/par/example_top.xpi
DDR2_Control/mig_37/example_design/par/example_top.xst
DDR2_Control/mig_37/example_design/par/example_top_bitgen.xwbt
DDR2_Control/mig_37/example_design/par/example_top_envsettings.html
DDR2_Control/mig_37/example_design/par/example_top_guide.ncd
DDR2_Control/mig_37/example_design/par/example_top_map.map
DDR2_Control/mig_37/example_design/par/example_top_map.mrp
DDR2_Control/mig_37/example_design/par/example_top_map.ncd
DDR2_Control/mig_37/example_design/par/example_top_map.ngm
DDR2_Control/mig_37/example_design/par/example_top_map.xrpt
DDR2_Control/mig_37/example_design/par/example_top_ngdbuild.xrpt
DDR2_Control/mig_37/example_design/par/example_top_pad.csv
DDR2_Control/mig_37/example_design/par/example_top_pad.txt
DDR2_Control/mig_37/example_design/par/example_top_par.xrpt
DDR2_Control/mig_37/example_design/par/example_top_summary.html
DDR2_Control/mig_37/example_design/par/example_top_summary.xml
DDR2_Control/mig_37/example_design/par/example_top_usage.xml
DDR2_Control/mig_37/example_design/par/example_top_xst.xrpt
DDR2_Control/mig_37/example_design/par/icon.asy
DDR2_Control/mig_37/example_design/par/icon.gise
DDR2_Control/mig_37/example_design/par/icon.ngc
DDR2_Control/mig_37/example_design/par/icon.xco
DDR2_Control/mig_37/example_design/par/icon.xise
DDR2_Control/mig_37/example_design/par/icon_coregen.xco
DDR2_Control/mig_37/example_design/par/icon_flist.txt
DDR2_Control/mig_37/example_design/par/icon_readme.txt
DDR2_Control/mig_37/example_design/par/icon_xmdf.tcl
DDR2_Control/mig_37/example_design/par/ila.cdc
DDR2_Control/mig_37/example_design/par/ila.gise
DDR2_Control/mig_37/example_design/par/ila.ngc
DDR2_Control/mig_37/example_design/par/ila.xco
DDR2_Control/mig_37/example_design/par/ila.xise
DDR2_Control/mig_37/example_design/par/ila_coregen.xco
DDR2_Control/mig_37/example_design/par/ila_flist.txt
DDR2_Control/mig_37/example_design/par/ila_readme.txt
DDR2_Control/mig_37/example_design/par/ila_xmdf.tcl
DDR2_Control/mig_37/example_design/par/ise_flow.bat
DDR2_Control/mig_37/example_design/par/ise_run.txt
DDR2_Control/mig_37/example_design/par/iseconfig/
DDR2_Control/mig_37/example_design/par/iseconfig/example_top.xreport
DDR2_Control/mig_37/example_design/par/iseconfig/test.projectmgr
DDR2_Control/mig_37/example_design/par/makeproj.bat
DDR2_Control/mig_37/example_design/par/mem_interface_top.ut
DDR2_Control/mig_37/example_design/par/pa.fromNetlist.tcl
DDR2_Control/mig_37/example_design/par/par_u

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