This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program

(GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very

efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time

constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and

rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design

over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also

variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation

that is compatible with GP or GGP.