文件名称:test51_PLL
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- 上传时间:2017-09-27
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文件大小:292kb
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下载文件列表
test51_PLL/component/
test51_PLL/component/work/
test51_PLL/component/work/DESIGN_FIRMWARE/
test51_PLL/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.cxf
test51_PLL/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.sdb
test51_PLL/component/work/DESIGN_IO/
test51_PLL/component/work/DESIGN_IO/DESIGN_IO.cxf
test51_PLL/component/work/DESIGN_IO/DESIGN_IO.sdb
test51_PLL/component/work/tb_top/
test51_PLL/component/work/tb_top/tb_top.cxf
test51_PLL/component/work/tb_top/tb_top.sdb
test51_PLL/component/work/tb_top/tb_top.vhd
test51_PLL/component/work/tb_top/tb_top_manifest.txt
test51_PLL/component/work/top/
test51_PLL/component/work/top/datasheet.xsl
test51_PLL/component/work/top/top.cxf
test51_PLL/component/work/top/top.sdb
test51_PLL/component/work/top/top_DataSheet.xml
test51_PLL/constraint/
test51_PLL/coreconsole/
test51_PLL/designer/
test51_PLL/designer/impl1/
test51_PLL/designer/impl1/designer_synth_check.log
test51_PLL/designer/impl1/simulation/
test51_PLL/designer/impl1/top.ide_des
test51_PLL/designer/impl1/top.tcl
test51_PLL/firmware/
test51_PLL/hdl/
test51_PLL/simulation/
test51_PLL/simulation/modelsim.ini
test51_PLL/simulation/postsynth/
test51_PLL/simulation/postsynth/_info
test51_PLL/simulation/postsynth/_lib.qdb
test51_PLL/simulation/postsynth/_lib1_0.qdb
test51_PLL/simulation/postsynth/_lib1_0.qpg
test51_PLL/simulation/postsynth/_lib1_0.qtl
test51_PLL/simulation/postsynth/_vmake
test51_PLL/simulation/run.do
test51_PLL/simulation/tb_top_postsynth_simulation.log
test51_PLL/simulation/vsim.wlf
test51_PLL/smartgen/
test51_PLL/smartgen/DESIGN_FIRMWARE_work.ixf
test51_PLL/smartgen/DESIGN_IO_work.ixf
test51_PLL/smartgen/PLL50M/
test51_PLL/smartgen/PLL50M/PLL50M.cxf
test51_PLL/smartgen/PLL50M/PLL50M.gen
test51_PLL/smartgen/PLL50M/PLL50M.log
test51_PLL/smartgen/PLL50M/PLL50M.vhd
test51_PLL/smartgen/PLL50M_work.ixf
test51_PLL/smartgen/smartgen.aws
test51_PLL/smartgen/tb_top_work.ixf
test51_PLL/smartgen/top_work.ixf
test51_PLL/stimulus/
test51_PLL/stimulus/tb_clk.vhd
test51_PLL/synthesis/
test51_PLL/synthesis/.recordref
test51_PLL/synthesis/backup/
test51_PLL/synthesis/backup/top.srr
test51_PLL/synthesis/coreip/
test51_PLL/synthesis/dm/
test51_PLL/synthesis/dm/layer0.xdm
test51_PLL/synthesis/run_options.txt
test51_PLL/synthesis/scratchproject.prs
test51_PLL/synthesis/synlog.tcl
test51_PLL/synthesis/synlog/
test51_PLL/synthesis/synlog/layer0.tlg.rptmap
test51_PLL/synthesis/synlog/report/
test51_PLL/synthesis/synlog/report/top_compiler_notes.txt
test51_PLL/synthesis/synlog/report/top_compiler_runstatus.xml
test51_PLL/synthesis/synlog/report/top_fpga_mapper_area_report.xml
test51_PLL/synthesis/synlog/report/top_fpga_mapper_combined_clk.rpt
test51_PLL/synthesis/synlog/report/top_fpga_mapper_errors.txt
test51_PLL/synthesis/synlog/report/top_fpga_mapper_notes.txt
test51_PLL/synthesis/synlog/report/top_fpga_mapper_opt_report.xml
test51_PLL/synthesis/synlog/report/top_fpga_mapper_resourceusage.rpt
test51_PLL/synthesis/synlog/report/top_fpga_mapper_runstatus.xml
test51_PLL/synthesis/synlog/report/top_fpga_mapper_timing_report.xml
test51_PLL/synthesis/synlog/report/top_fpga_mapper_warnings.txt
test51_PLL/synthesis/synlog/report/top_premap_errors.txt
test51_PLL/synthesis/synlog/report/top_premap_notes.txt
test51_PLL/synthesis/synlog/report/top_premap_runstatus.xml
test51_PLL/synthesis/synlog/report/top_premap_warnings.txt
test51_PLL/synthesis/synlog/syntax_constraint_check.rpt.rptmap
test51_PLL/synthesis/synlog/top_compiler.srr
test51_PLL/synthesis/synlog/top_compiler.srr.rptmap
test51_PLL/synthesis/synlog/top_fpga_mapper.srr
test51_PLL/synthesis/synlog/top_fpga_mapper.szr
test51_PLL/synthesis/synlog/top_multi_srs_gen.srr
test51_PLL/synthesis/synlog/top_premap.srr
test51_PLL/synthesis/synlog/top_premap.szr
test51_PLL/synthesis/synplify.log
test51_PLL/synthesis/syntmp/
test51_PLL/synthesis/syntmp/closed.png
test51_PLL/synthesis/syntmp/cmdrec_compiler.log
test51_PLL/synthesis/syntmp/cmdrec_fpga_mapper.log
test51_PLL/synthesis/syntmp/cmdrec_multi_srs_gen.log
test51_PLL/synthesis/syntmp/cmdrec_premap.log
test51_PLL/synthesis/syntmp/open.png
test51_PLL/synthesis/syntmp/run_option.xml
test51_PLL/synthesis/syntmp/statusReport.html
test51_PLL/synthesis/syntmp/top.plg
test51_PLL/synthesis/syntmp/top_srr.htm
test51_PLL/synthesis/syntmp/top_toc.htm
test51_PLL/synthesis/synwork/
test51_PLL/synthesis/synwork/.cckTransfer
test51_PLL/synthesis/synwork/_mh_info
test51_PLL/synthesis/synwork/layer0.fdep
test51_PLL/synthesis/synwork/layer0.fdeporig
test51_PLL/synthesis/synwork/layer0.srs
test51_PLL/synthesis/synwork/layer0.tlg
test51_PLL/synthesis/synwork/top_comp.fdep
test51_PLL/synthesis/synwork/top_comp.srs
test51_PLL/synthesis/synwork/top_m.srm
test51_PLL/synthesis/synwork/top_m_srm/
test51_PLL/synthesis/synwork/top_m_srm/1.srm
test51_PLL/synthesis/synwork/top_m_srm/fileinfo.srm
test51_PLL/synthesis/synwork/top_mult.srs
test51_PLL/synthesis/synwork/top_mult_srs/
test51_PLL/synthesis/synwork/top_mult_srs/1.srs
test51_PLL/synthesis/synwork/top_mult_srs/fileinfo.srs
test51_PLL/synthesis/synwork/top_mult_srs/skeleton.srs
test51_PLL/synthesis/synwork/top_prem.fse
test51_PLL/component/work/
test51_PLL/component/work/DESIGN_FIRMWARE/
test51_PLL/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.cxf
test51_PLL/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.sdb
test51_PLL/component/work/DESIGN_IO/
test51_PLL/component/work/DESIGN_IO/DESIGN_IO.cxf
test51_PLL/component/work/DESIGN_IO/DESIGN_IO.sdb
test51_PLL/component/work/tb_top/
test51_PLL/component/work/tb_top/tb_top.cxf
test51_PLL/component/work/tb_top/tb_top.sdb
test51_PLL/component/work/tb_top/tb_top.vhd
test51_PLL/component/work/tb_top/tb_top_manifest.txt
test51_PLL/component/work/top/
test51_PLL/component/work/top/datasheet.xsl
test51_PLL/component/work/top/top.cxf
test51_PLL/component/work/top/top.sdb
test51_PLL/component/work/top/top_DataSheet.xml
test51_PLL/constraint/
test51_PLL/coreconsole/
test51_PLL/designer/
test51_PLL/designer/impl1/
test51_PLL/designer/impl1/designer_synth_check.log
test51_PLL/designer/impl1/simulation/
test51_PLL/designer/impl1/top.ide_des
test51_PLL/designer/impl1/top.tcl
test51_PLL/firmware/
test51_PLL/hdl/
test51_PLL/simulation/
test51_PLL/simulation/modelsim.ini
test51_PLL/simulation/postsynth/
test51_PLL/simulation/postsynth/_info
test51_PLL/simulation/postsynth/_lib.qdb
test51_PLL/simulation/postsynth/_lib1_0.qdb
test51_PLL/simulation/postsynth/_lib1_0.qpg
test51_PLL/simulation/postsynth/_lib1_0.qtl
test51_PLL/simulation/postsynth/_vmake
test51_PLL/simulation/run.do
test51_PLL/simulation/tb_top_postsynth_simulation.log
test51_PLL/simulation/vsim.wlf
test51_PLL/smartgen/
test51_PLL/smartgen/DESIGN_FIRMWARE_work.ixf
test51_PLL/smartgen/DESIGN_IO_work.ixf
test51_PLL/smartgen/PLL50M/
test51_PLL/smartgen/PLL50M/PLL50M.cxf
test51_PLL/smartgen/PLL50M/PLL50M.gen
test51_PLL/smartgen/PLL50M/PLL50M.log
test51_PLL/smartgen/PLL50M/PLL50M.vhd
test51_PLL/smartgen/PLL50M_work.ixf
test51_PLL/smartgen/smartgen.aws
test51_PLL/smartgen/tb_top_work.ixf
test51_PLL/smartgen/top_work.ixf
test51_PLL/stimulus/
test51_PLL/stimulus/tb_clk.vhd
test51_PLL/synthesis/
test51_PLL/synthesis/.recordref
test51_PLL/synthesis/backup/
test51_PLL/synthesis/backup/top.srr
test51_PLL/synthesis/coreip/
test51_PLL/synthesis/dm/
test51_PLL/synthesis/dm/layer0.xdm
test51_PLL/synthesis/run_options.txt
test51_PLL/synthesis/scratchproject.prs
test51_PLL/synthesis/synlog.tcl
test51_PLL/synthesis/synlog/
test51_PLL/synthesis/synlog/layer0.tlg.rptmap
test51_PLL/synthesis/synlog/report/
test51_PLL/synthesis/synlog/report/top_compiler_notes.txt
test51_PLL/synthesis/synlog/report/top_compiler_runstatus.xml
test51_PLL/synthesis/synlog/report/top_fpga_mapper_area_report.xml
test51_PLL/synthesis/synlog/report/top_fpga_mapper_combined_clk.rpt
test51_PLL/synthesis/synlog/report/top_fpga_mapper_errors.txt
test51_PLL/synthesis/synlog/report/top_fpga_mapper_notes.txt
test51_PLL/synthesis/synlog/report/top_fpga_mapper_opt_report.xml
test51_PLL/synthesis/synlog/report/top_fpga_mapper_resourceusage.rpt
test51_PLL/synthesis/synlog/report/top_fpga_mapper_runstatus.xml
test51_PLL/synthesis/synlog/report/top_fpga_mapper_timing_report.xml
test51_PLL/synthesis/synlog/report/top_fpga_mapper_warnings.txt
test51_PLL/synthesis/synlog/report/top_premap_errors.txt
test51_PLL/synthesis/synlog/report/top_premap_notes.txt
test51_PLL/synthesis/synlog/report/top_premap_runstatus.xml
test51_PLL/synthesis/synlog/report/top_premap_warnings.txt
test51_PLL/synthesis/synlog/syntax_constraint_check.rpt.rptmap
test51_PLL/synthesis/synlog/top_compiler.srr
test51_PLL/synthesis/synlog/top_compiler.srr.rptmap
test51_PLL/synthesis/synlog/top_fpga_mapper.srr
test51_PLL/synthesis/synlog/top_fpga_mapper.szr
test51_PLL/synthesis/synlog/top_multi_srs_gen.srr
test51_PLL/synthesis/synlog/top_premap.srr
test51_PLL/synthesis/synlog/top_premap.szr
test51_PLL/synthesis/synplify.log
test51_PLL/synthesis/syntmp/
test51_PLL/synthesis/syntmp/closed.png
test51_PLL/synthesis/syntmp/cmdrec_compiler.log
test51_PLL/synthesis/syntmp/cmdrec_fpga_mapper.log
test51_PLL/synthesis/syntmp/cmdrec_multi_srs_gen.log
test51_PLL/synthesis/syntmp/cmdrec_premap.log
test51_PLL/synthesis/syntmp/open.png
test51_PLL/synthesis/syntmp/run_option.xml
test51_PLL/synthesis/syntmp/statusReport.html
test51_PLL/synthesis/syntmp/top.plg
test51_PLL/synthesis/syntmp/top_srr.htm
test51_PLL/synthesis/syntmp/top_toc.htm
test51_PLL/synthesis/synwork/
test51_PLL/synthesis/synwork/.cckTransfer
test51_PLL/synthesis/synwork/_mh_info
test51_PLL/synthesis/synwork/layer0.fdep
test51_PLL/synthesis/synwork/layer0.fdeporig
test51_PLL/synthesis/synwork/layer0.srs
test51_PLL/synthesis/synwork/layer0.tlg
test51_PLL/synthesis/synwork/top_comp.fdep
test51_PLL/synthesis/synwork/top_comp.srs
test51_PLL/synthesis/synwork/top_m.srm
test51_PLL/synthesis/synwork/top_m_srm/
test51_PLL/synthesis/synwork/top_m_srm/1.srm
test51_PLL/synthesis/synwork/top_m_srm/fileinfo.srm
test51_PLL/synthesis/synwork/top_mult.srs
test51_PLL/synthesis/synwork/top_mult_srs/
test51_PLL/synthesis/synwork/top_mult_srs/1.srs
test51_PLL/synthesis/synwork/top_mult_srs/fileinfo.srs
test51_PLL/synthesis/synwork/top_mult_srs/skeleton.srs
test51_PLL/synthesis/synwork/top_prem.fse
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