PLL，即锁相环。是FPGA中的重要资源。由于一个复杂的FPGA系统往往需要多个不同频率，相位的时钟信号。所以，一个FPGA芯片中PLL的数量是衡量FPGA芯片能力的重要指标。FPGA的设计中，时钟系统的FPGA高速的设计极其重要，一个低抖动, 低延迟的系统时钟会增加FPGA设计的成功率。本例程调用Xilinx提供的PLL核来产生不同频率的时钟, 并把其中的一个时钟输出到FPGA外部IO上, 也就是开发板的SMA接口上。(PLL, pll. It's an important resource in FPGA. Because a complex FPGA system often requires multiple clock signals with different frequencies and phases. Therefore, the number of PLL in a FPGA chip is an important indicator of the ability of FPGA chip. In the design of FPGA, the high speed design of clock system FPGA is extremely important. A low jitter and low delay system clock will increase the success rate of FPGA design. This routine calls the PLL core provided by Xilinx to generate clocks of different frequencies, and outputs one of the clocks to the external IO of the FPGA, that is, the SMA interface of the development board.)