① Verilog的抽象级别

② Verilog的模块化设计

③ 如何给端口选择正确的数据类型

④ Verilog语言中latch的产生

⑤ 组合逻辑反馈环

⑥ 阻塞赋值与非阻塞赋值的不同

⑦ FPGA的灵魂状态机

⑧ 代码风格的重要性((1) the abstract level of Verilog
The modular design of Verilog
How to select the correct data type for the port
(4) the generation of latch in Verilog language
Combinational logic feedback loop
The blocking and nonblocking assignment assignment different
The soul of state machine FPGA
The importance of the code style)