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文件名称:ds1wm FPGA代码

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    2018-06-05
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    248.07kb
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ds1wm的FPGA代码,包括VHDL和Verilog,带验证
相关搜索: ds1wm

(系统自动生成,下载前可以参看下载内容)

下载文件列表

压缩包 : ds1wm.zip 列表
delivery/
delivery/design/
delivery/design/verilog_src/
delivery/design/verilog_src/ds1wm/
delivery/design/verilog_src/ds1wm/clk_prescaler.v
delivery/design/verilog_src/ds1wm/ds1wm.v
delivery/design/verilog_src/ds1wm/onewiremaster.v
delivery/design/verilog_src/ds1wm/one_wire_interface.v
delivery/design/verilog_src/ds1wm/one_wire_io.v
delivery/design/vhdl_src/
delivery/design/vhdl_src/ds1wm/
delivery/design/vhdl_src/ds1wm/clk_prescaler.vhd
delivery/design/vhdl_src/ds1wm/ds1wm.vhd
delivery/design/vhdl_src/ds1wm/onewiremaster.vhd
delivery/design/vhdl_src/ds1wm/one_wire_interface.vhd
delivery/design/vhdl_src/ds1wm/one_wire_io.vhd
delivery/doc/
delivery/doc/DS1WM_Datasheet.pdf
delivery/doc/release_notes.pdf
delivery/README
delivery/verification/
delivery/verification/verilog_src/
delivery/verification/verilog_src/testbench/
delivery/verification/verilog_src/testbench/clkgen/
delivery/verification/verilog_src/testbench/clkgen/clkgen.v
delivery/verification/verilog_src/testbench/cpu_bfm/
delivery/verification/verilog_src/testbench/cpu_bfm/cpu_bfm.v
delivery/verification/verilog_src/testbench/ow_slave/
delivery/verification/verilog_src/testbench/ow_slave/cmd_ctrl.v
delivery/verification/verilog_src/testbench/ow_slave/iox.v
delivery/verification/verilog_src/testbench/ow_slave/ow_slave.v
delivery/verification/verilog_src/testbench/scoreboard/
delivery/verification/verilog_src/testbench/scoreboard/scoreboard.v
delivery/verification/verilog_src/testbench/tb_ds1wm/
delivery/verification/verilog_src/testbench/tb_ds1wm/tb_ds1wm.v
delivery/verification/verilog_src/testbench/tb_ds1wm/tc_ds1wm.v
delivery/verification/verilog_src/tests/
delivery/verification/verilog_src/tests/cmd_recognition/
delivery/verification/verilog_src/tests/cmd_recognition/nc_rundir/
delivery/verification/verilog_src/tests/cmd_recognition/nc_rundir/cds.lib
delivery/verification/verilog_src/tests/cmd_recognition/nc_rundir/design_verilog_src_files.lst
delivery/verification/verilog_src/tests/cmd_recognition/nc_rundir/design_vhdl_src_files.lst
delivery/verification/verilog_src/tests/cmd_recognition/nc_rundir/hdl.var
delivery/verification/verilog_src/tests/cmd_recognition/nc_rundir/ncsim.key
delivery/verification/verilog_src/tests/cmd_recognition/nc_rundir/probe.tcl
delivery/verification/verilog_src/tests/cmd_recognition/nc_rundir/run.csh
delivery/verification/verilog_src/tests/cmd_recognition/nc_rundir/tb_src_files.lst
delivery/verification/verilog_src/tests/cmd_recognition/README
delivery/verification/verilog_src/tests/cmd_recognition/stimulus.inc
delivery/verification/verilog_src/tests/multi_ow_network/
delivery/verification/verilog_src/tests/multi_ow_network/nc_rundir/
delivery/verification/verilog_src/tests/multi_ow_network/nc_rundir/cds.lib
delivery/verification/verilog_src/tests/multi_ow_network/nc_rundir/design_verilog_src_files.lst
delivery/verification/verilog_src/tests/multi_ow_network/nc_rundir/design_vhdl_src_files.lst
delivery/verification/verilog_src/tests/multi_ow_network/nc_rundir/hdl.var
delivery/verification/verilog_src/tests/multi_ow_network/nc_rundir/ncsim.key
delivery/verification/verilog_src/tests/multi_ow_network/nc_rundir/probe.tcl
delivery/verification/verilog_src/tests/multi_ow_network/nc_rundir/run.csh
delivery/verification/verilog_src/tests/multi_ow_network/nc_rundir/tb_src_files.lst
delivery/verification/verilog_src/tests/multi_ow_network/README
delivery/verification/verilog_src/tests/multi_ow_network/stimulus.inc
delivery/verification/verilog_src/tests/scratchpad_integrity/
delivery/verification/verilog_src/tests/scratchpad_integrity/nc_rundir/
delivery/verification/verilog_src/tests/scratchpad_integrity/nc_rundir/cds.lib
delivery/verification/verilog_src/tests/scratchpad_integrity/nc_rundir/design_verilog_src_files.lst
delivery/verification/verilog_src/tests/scratchpad_integrity/nc_rundir/design_vhdl_src_files.lst
delivery/verification/verilog_src/tests/scratchpad_integrity/nc_rundir/hdl.var
delivery/verification/verilog_src/tests/scratchpad_integrity/nc_rundir/ncsim.key
delivery/verification/verilog_src/tests/scratchpad_integrity/nc_rundir/probe.tcl
delivery/verification/verilog_src/tests/scratchpad_integrity/nc_rundir/run.csh
delivery/verification/verilog_src/tests/scratchpad_integrity/nc_rundir/tb_src_files.lst
delivery/verification/verilog_src/tests/scratchpad_integrity/README
delivery/verification/verilog_src/tests/scratchpad_integrity/stimulus.inc
delivery/verification/verilog_src/tests/single_search_rom/
delivery/verification/verilog_src/tests/single_search_rom/nc_rundir/
delivery/verification/verilog_src/tests/single_search_rom/nc_rundir/cds.lib
delivery/verification/verilog_src/tests/single_search_rom/nc_rundir/design_verilog_src_files.lst
delivery/verification/verilog_src/tests/single_search_rom/nc_rundir/design_vhdl_src_files.lst
delivery/verification/verilog_src/tests/single_search_rom/nc_rundir/hdl.var
delivery/verification/verilog_src/tests/single_search_rom/nc_rundir/ncsim.key
delivery/verification/verilog_src/tests/single_search_rom/nc_rundir/probe.tcl
delivery/verification/verilog_src/tests/single_search_rom/nc_rundir/run.csh

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