示例说明.doc
Altera_lib_files/220model.txt
Altera_lib_files/220model.v
Altera_lib_files/220model.vhd
Altera_lib_files/220model_87.vhd
Altera_lib_files/220pack.vhd
Altera_lib_files/altera_mf.txt
Altera_lib_files/altera_mf.v
Altera_lib_files/altera_mf.vhd
Altera_lib_files/altera_mf_87.vhd
Altera_lib_files/altera_mf_components.vhd
Altera_lib_files/stratix_atoms.v
Altera_lib_files/stratix_atoms.vhd
Altera_lib_files/stratix_components.vhd
func_sim/dpram8x32.v
func_sim/func_sim.cr.mti
func_sim/func_sim.mpf
func_sim/func_sim_wave.wlf
func_sim/pllx2.v
func_sim/pll_ram.v
func_sim/pll_ram_tb.v
func_sim/transcript
func_sim/vsim.wlf
func_sim/wave.bmp
func_sim/wave.do
func_sim/work/dpram8x32/verilog.asm
func_sim/work/dpram8x32/_primary.dat
func_sim/work/dpram8x32/_primary.vhd
func_sim/work/pllx2/verilog.asm
func_sim/work/pllx2/_primary.dat
func_sim/work/pllx2/_primary.vhd
func_sim/work/pll_ram/verilog.asm
func_sim/work/pll_ram/_primary.dat
func_sim/work/pll_ram/_primary.vhd
func_sim/work/pll_ram_tb/verilog.asm
func_sim/work/pll_ram_tb/_primary.dat
func_sim/work/pll_ram_tb/_primary.vhd
func_sim/work/_info
pll_ram/cmp_state.ini
pll_ram/db/altsyncram_7bc1.tdf
pll_ram/db/pll_ram(0).cnf.cdb
pll_ram/db/pll_ram(0).cnf.hdb
pll_ram/db/pll_ram(1).cnf.cdb
pll_ram/db/pll_ram(1).cnf.hdb
pll_ram/db/pll_ram(2).cnf.cdb
pll_ram/db/pll_ram(2).cnf.hdb
pll_ram/db/pll_ram(3).cnf.cdb
pll_ram/db/pll_ram(3).cnf.hdb
pll_ram/db/pll_ram(4).cnf.cdb
pll_ram/db/pll_ram(4).cnf.hdb
pll_ram/db/pll_ram(5).cnf.cdb
pll_ram/db/pll_ram(5).cnf.hdb
pll_ram/db/pll_ram(6).cnf.cdb
pll_ram/db/pll_ram(6).cnf.hdb
pll_ram/db/pll_ram(7).cnf.cdb
pll_ram/db/pll_ram(7).cnf.hdb
pll_ram/db/pll_ram.asm.qmsg
pll_ram/db/pll_ram.cmp.cdb
pll_ram/db/pll_ram.cmp.ddb
pll_ram/db/pll_ram.cmp.hdb
pll_ram/db/pll_ram.cmp.rdb
pll_ram/db/pll_ram.cmp.tdb
pll_ram/db/pll_ram.csf.qmsg
pll_ram/db/pll_ram.db_info
pll_ram/db/pll_ram.eda.qmsg
pll_ram/db/pll_ram.fit.qmsg
pll_ram/db/pll_ram.hif
pll_ram/db/pll_ram.icc
pll_ram/db/pll_ram.map.cdb
pll_ram/db/pll_ram.map.hdb
pll_ram/db/pll_ram.map.qmsg
pll_ram/db/pll_ram.pll_ram.sld_design_entry.sci
pll_ram/db/pll_ram.pre_map.hdb
pll_ram/db/pll_ram.project.hdb
pll_ram/db/pll_ram.rtlv.hdb
pll_ram/db/pll_ram.rtlv_sg.cdb
pll_ram/db/pll_ram.rtlv_sg_swap.cdb
pll_ram/db/pll_ram.sgdiff.cdb
pll_ram/db/pll_ram.sgdiff.hdb
pll_ram/db/pll_ram.signalprobe.cdb
pll_ram/db/pll_ram.tan.qmsg
pll_ram/db/pll_ram_cmp.qrpt
pll_ram/db/pll_ram_hier_info
pll_ram/db/pll_ram_syn_hier_info
pll_ram/dpram8x32.v
pll_ram/pllx2.v
pll_ram/pll_ram.asm.rpt
pll_ram/pll_ram.done
pll_ram/pll_ram.eda.rpt
pll_ram/pll_ram.fit.eqn
pll_ram/pll_ram.fit.rpt
pll_ram/pll_ram.flow.rpt
pll_ram/pll_ram.map.eqn
pll_ram/pll_ram.map.rpt
pll_ram/pll_ram.pin
pll_ram/pll_ram.pof
pll_ram/pll_ram.qpf
pll_ram/pll_ram.qsf
pll_ram/pll_ram.qws
pll_ram/pll_ram.sof
pll_ram/pll_ram.tan.rpt
pll_ram/pll_ram.tan.summary
pll_ram/pll_ram.v
pll_ram/simulation/modelsim/pll_ram.vo
pll_ram/simulation/modelsim/pll_ram_modelsim.xrf
pll_ram/simulation/modelsim/pll_ram_v.sdo
source/dpram8x32.v
source/dpram8x32_bb.v
source/dpram8x32_wave0.jpg
source/dpram8x32_wave1.jpg
source/dpram8x32_wave2.jpg
source/dpram8x32_wave3.jpg
source/dpram8x32_waveforms.html
source/pllx2.v
source/pllx2_bb.v
source/pll_ram.v
source/pll_ram_tb.v
source/post-simulation/modelsim/pll_ram.vo
source/post-simulation/modelsim/pll_ram_modelsim.xrf
source/post-simulation/modelsim/pll_ram_v.sdo
timing_sim/pll_ram.vo
timing_sim/pll_ram_modelsim.xrf
timing_sim/pll_ram_tb.v
timing_sim/pll_ram_v.sdo
timing_sim/timing_sim.cr.mti
timing_sim/timing_sim.mpf
timing_sim/transcript
timing_sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
timing_sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
timing_sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
timing_sim/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
timing_sim/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
timing_sim/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
timing_sim/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.asm
timing_sim/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
timing_sim/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
timing_sim/work/@m@f_pll_reg/verilog.asm
timing_sim/work/@m@f_pll_reg/_primary.dat
timing_sim/work/@m@f_pll_reg/_primary.vhd
timing_sim/work/@m@f_ram7x20_syn/verilog.asm
timing_sim/work/@m@f_ram7x20_syn/_primary.dat
timing_sim/work/@m@f_ram7x20_syn/_primary.vhd
timing_sim/work/@m@f_stratixii_pll/verilog.asm
timing_sim/work/@m@f_stratixii_pll/_primary.dat
timing_sim/work/@m@f_stratixii_pll/_primary.vhd
timing_sim/work/@m@f_stratix_pll/verilog.asm
timing_sim/work/@m@f_stratix_pll/_primary.dat
timing_sim/work/@m@f_stratix_pll/_primary.vhd
timing_sim/work/@p@r@i@m_@d@f@f@e/verilog.asm
timing_sim/work/@p@r@i@m_@d@f@f@e/_primary.dat
timing_sim/work/@p@r@i@m_@d@f@f@e/_primary.vhd
timing_sim/work/alt3pram/verilog.asm
timing_sim/work/alt3pram/_primary.dat
timing_sim/work/alt3pram/_primary.vhd
timing_sim/work/altaccumulate/verilog.asm
timing_sim/work/altaccumulate/_primary.dat
timing_sim/work/altaccumulate/_primary.vhd
timing_sim/