fpga/使用说明.txt
fpga/Chapter9 Sample/使用说明.txt
fpga/Chapter9 Sample/canbus/.untf
fpga/Chapter9 Sample/canbus/can_acf.v
fpga/Chapter9 Sample/canbus/can_bsp.v
fpga/Chapter9 Sample/canbus/can_btl.v
fpga/Chapter9 Sample/canbus/can_crc.v
fpga/Chapter9 Sample/canbus/can_defines.v
fpga/Chapter9 Sample/canbus/can_fifo.cmd_log
fpga/Chapter9 Sample/canbus/can_fifo.lso
fpga/Chapter9 Sample/canbus/can_fifo.ngc
fpga/Chapter9 Sample/canbus/can_fifo.ngr
fpga/Chapter9 Sample/canbus/can_fifo.prj
fpga/Chapter9 Sample/canbus/can_fifo.stx
fpga/Chapter9 Sample/canbus/can_fifo.syr
fpga/Chapter9 Sample/canbus/can_fifo.v
fpga/Chapter9 Sample/canbus/can_fifo_vhdl.prj
fpga/Chapter9 Sample/canbus/can_ibo.v
fpga/Chapter9 Sample/canbus/can_register.v
fpga/Chapter9 Sample/canbus/can_register_asyn.v
fpga/Chapter9 Sample/canbus/can_register_asyn_syn.cmd_log
fpga/Chapter9 Sample/canbus/can_register_asyn_syn.lso
fpga/Chapter9 Sample/canbus/can_register_asyn_syn.ngc
fpga/Chapter9 Sample/canbus/can_register_asyn_syn.ngr
fpga/Chapter9 Sample/canbus/can_register_asyn_syn.prj
fpga/Chapter9 Sample/canbus/can_register_asyn_syn.stx
fpga/Chapter9 Sample/canbus/can_register_asyn_syn.syr
fpga/Chapter9 Sample/canbus/can_register_asyn_syn.v
fpga/Chapter9 Sample/canbus/can_register_asyn_syn_vhdl.prj
fpga/Chapter9 Sample/canbus/can_register_syn.v
fpga/Chapter9 Sample/canbus/can_registers.lso
fpga/Chapter9 Sample/canbus/can_registers.prj
fpga/Chapter9 Sample/canbus/can_registers.stx
fpga/Chapter9 Sample/canbus/can_registers.v
fpga/Chapter9 Sample/canbus/can_registers_vhdl.prj
fpga/Chapter9 Sample/canbus/can_testbench.fdo
fpga/Chapter9 Sample/canbus/can_testbench.ndo
fpga/Chapter9 Sample/canbus/can_testbench.udo
fpga/Chapter9 Sample/canbus/can_testbench.v
fpga/Chapter9 Sample/canbus/can_testbench_defines.v
fpga/Chapter9 Sample/canbus/can_top.bld
fpga/Chapter9 Sample/canbus/can_top.cmd_log
fpga/Chapter9 Sample/canbus/can_top.ldo
fpga/Chapter9 Sample/canbus/can_top.lso
fpga/Chapter9 Sample/canbus/can_top.ngc
fpga/Chapter9 Sample/canbus/can_top.ngd
fpga/Chapter9 Sample/canbus/can_top.ngr
fpga/Chapter9 Sample/canbus/can_top.prj
fpga/Chapter9 Sample/canbus/can_top.stx
fpga/Chapter9 Sample/canbus/can_top.syr
fpga/Chapter9 Sample/canbus/can_top.v
fpga/Chapter9 Sample/canbus/can_top.vhdsim_xlate
fpga/Chapter9 Sample/canbus/can_top.xlate_nlf
fpga/Chapter9 Sample/canbus/can_top_translate.nlf
fpga/Chapter9 Sample/canbus/can_top_translate.vhd
fpga/Chapter9 Sample/canbus/can_top_vhdl.prj
fpga/Chapter9 Sample/canbus/canbus.dhp
fpga/Chapter9 Sample/canbus/canbus.npl
fpga/Chapter9 Sample/canbus/coregen.prj
fpga/Chapter9 Sample/canbus/prjname.lso
fpga/Chapter9 Sample/canbus/timescale.v
fpga/Chapter9 Sample/canbus/transcript
fpga/Chapter9 Sample/canbus/__projnav/can_fifo.xst
fpga/Chapter9 Sample/canbus/__projnav/can_register_asyn_syn.xst
fpga/Chapter9 Sample/canbus/__projnav/can_registers.xst
fpga/Chapter9 Sample/canbus/__projnav/can_top.xst
fpga/Chapter9 Sample/canbus/__projnav/canbus.gfl
fpga/Chapter9 Sample/canbus/__projnav/canbus_flowplus.gfl
fpga/Chapter9 Sample/canbus/__projnav/coregen.rsp
fpga/Chapter9 Sample/canbus/__projnav/ednTOngd_tcl.rsp
fpga/Chapter9 Sample/canbus/__projnav/runXst_tcl.rsp
fpga/Chapter9 Sample/canbus/__projnav/xst_sprjTOstx_tcl.rsp
fpga/Chapter9 Sample/canbus/_ngo/netlist.lst
fpga/Chapter9 Sample/canbus/work/_info
fpga/Chapter9 Sample/canbus/work/can_acf/_primary.dat
fpga/Chapter9 Sample/canbus/work/can_acf/_primary.vhd
fpga/Chapter9 Sample/canbus/work/can_acf/verilog.asm
fpga/Chapter9 Sample/canbus/work/can_bsp/_primary.dat
fpga/Chapter9 Sample/canbus/work/can_bsp/_primary.vhd
fpga/Chapter9 Sample/canbus/work/can_bsp/verilog.asm
fpga/Chapter9 Sample/canbus/work/can_btl/_primary.dat
fpga/Chapter9 Sample/canbus/work/can_btl/_primary.vhd
fpga/Chapter9 Sample/canbus/work/can_btl/verilog.asm
fpga/Chapter9 Sample/canbus/work/can_crc/_primary.dat
fpga/Chapter9 Sample/canbus/work/can_crc/_primary.vhd
fpga/Chapter9 Sample/canbus/work/can_crc/verilog.asm
fpga/Chapter9 Sample/canbus/work/can_fifo/_primary.dat
fpga/Chapter9 Sample/canbus/work/can_fifo/_primary.vhd
fpga/Chapter9 Sample/canbus/work/can_fifo/verilog.asm
fpga/Chapter9 Sample/canbus/work/can_ibo/_primary.dat
fpga/Chapter9 Sample/canbus/work/can_ibo/_primary.vhd
fpga/Chapter9 Sample/canbus/work/can_ibo/verilog.asm
fpga/Chapter9 Sample/canbus/work/can_register/_primary.dat
fpga/Chapter9 Sample/canbus/work/can_register/_primary.vhd
fpga/Chapter9 Sample/canbus/work/can_register/verilog.asm
fpga/Chapter9 Sample/canbus/work/can_register_asyn/_primary.dat
fpga/Chapter9 Sample/canbus/work/can_register_asyn/_primary.vhd
fpga/Chapter9 Sample/canbus/work/can_register_asyn/verilog.asm
fpga/Chapter9 Sample/canbus/work/can_register_asyn_syn/_primary.dat
fpga/Chapter9 Sample/canbus/work/can_register_asyn_syn/_primary.vhd
fpga/Chapter9 Sample/canbus/work/can_register_asyn_syn/verilog.asm
fpga/Chapter9 Sample/canbus/work/can_registers/_primary.dat
fpga/Chapter9 Sample/canbus/work/can_registers/_primary.vhd
fpga/Chapter9 Sample/canbus/work/can_registers/verilog.asm
fpga/Chapter9 Sample/canbus/work/can_testbench/_primary.dat
fpga/Chap