文件名称:rs232_vhd
介绍说明--下载内容来自于网络,使用问题请自行百度
此RS232通信协议用VHDL语言实现,基于Altium Designer公司的Protel DXP开发平台。本人是基于Nanaboard开发板编写的程序,其他用户只需要对配置文件进行修改即可用于其他电路板。
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下载文件列表
rs232_完整版/baud.vhd
rs232_完整版/baud.vhdPreview
rs232_完整版/FPGA_Project2.PrjFpg
rs232_完整版/FPGA_Project2.PrjFpgStructure
rs232_完整版/reciever.vhd
rs232_完整版/reciever.vhdPreview
rs232_完整版/rs232_UART.vhd
rs232_完整版/Sheet2 SCH ECO 2008-7-29 11-36-13.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-29 13-58-21.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-29 16-20-23.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 13-20-27.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 8-12-06.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 8-27-29.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 8-34-57.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 8-47-21.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 9-33-02.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 9-38-17.LOG
rs232_完整版/Sheet2.SchDoc
rs232_完整版/Sheet2.SchDocPreview
rs232_完整版/transfer.vhd
rs232_完整版/transfer.vhdPreview
rs232_完整版/ProjectOutputs/Sheet2.VHD
rs232_完整版/ProjectOutputs/Sheet2.VHDPreview
rs232_完整版/ProjectOutputs/rs232_v2/configurable_u1.VHD
rs232_完整版/ProjectOutputs/rs232_v2/configurable_u3.VHD
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.asm.rpt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.bfl
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.edn
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.fit.eqn
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.fit.rpt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.fit.summary
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.FIT.~.EQN
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.flow.rpt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.FlwCmp
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.hexout
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.jam
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.jbc
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.map.eqn
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.map.rpt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.map.summary
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.MAP.~.EQN
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.mof
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.mpf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.pin
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.pof
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.qpf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.qpf_orig
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.qsf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.rbf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.sof
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.svf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.tan.rpt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.tan.summary
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.TCLQ
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.ttf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.~.qpf_orig
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.~.RBF
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_constraints.tcl
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_ConstraintsEx.TCL
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_CoreGen.txt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_epc.jam
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_epc.jbc
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_epc.svf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_MacroFiles.tcl
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_MacroSettings.tcl
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_sta.SDC
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_Synth.log
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_UserConstraints.TCL
rs232_完整版/ProjectOutputs/rs232_v2/FRQCNT2.VQM
rs232_完整版/ProjectOutputs/rs232_v2/J8S_8B.VHD
rs232_完整版/ProjectOutputs/rs232_v2/LPM_COMPARE_32_32.dep
rs232_完整版/ProjectOutputs/rs232_v2/LPM_COMPARE_32_32.vhd
rs232_完整版/ProjectOutputs/rs232_v2/Sheet2.VHD
rs232_完整版/ProjectOutputs/rs232_v2/Status Report.Txt
rs232_完整版/ProjectOutputs/rs232_v2/_blf/baud_body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/baud_header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_10__body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_10__header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_16__body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_16__header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_1__body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_1__header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_8__body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_8__header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DRNOOUT_32__body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DRNOOUT_32__header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_TAPCONTROLLER_body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_TAPCONTROLLER_header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1_body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1_header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16
rs232_完整版/baud.vhdPreview
rs232_完整版/FPGA_Project2.PrjFpg
rs232_完整版/FPGA_Project2.PrjFpgStructure
rs232_完整版/reciever.vhd
rs232_完整版/reciever.vhdPreview
rs232_完整版/rs232_UART.vhd
rs232_完整版/Sheet2 SCH ECO 2008-7-29 11-36-13.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-29 13-58-21.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-29 16-20-23.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 13-20-27.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 8-12-06.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 8-27-29.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 8-34-57.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 8-47-21.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 9-33-02.LOG
rs232_完整版/Sheet2 SCH ECO 2008-7-30 9-38-17.LOG
rs232_完整版/Sheet2.SchDoc
rs232_完整版/Sheet2.SchDocPreview
rs232_完整版/transfer.vhd
rs232_完整版/transfer.vhdPreview
rs232_完整版/ProjectOutputs/Sheet2.VHD
rs232_完整版/ProjectOutputs/Sheet2.VHDPreview
rs232_完整版/ProjectOutputs/rs232_v2/configurable_u1.VHD
rs232_完整版/ProjectOutputs/rs232_v2/configurable_u3.VHD
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.asm.rpt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.bfl
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.edn
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.fit.eqn
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.fit.rpt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.fit.summary
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.FIT.~.EQN
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.flow.rpt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.FlwCmp
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.hexout
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.jam
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.jbc
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.map.eqn
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.map.rpt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.map.summary
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.MAP.~.EQN
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.mof
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.mpf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.pin
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.pof
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.qpf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.qpf_orig
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.qsf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.rbf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.sof
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.svf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.tan.rpt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.tan.summary
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.TCLQ
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.ttf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.~.qpf_orig
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2.~.RBF
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_constraints.tcl
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_ConstraintsEx.TCL
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_CoreGen.txt
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_epc.jam
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_epc.jbc
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_epc.svf
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_MacroFiles.tcl
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_MacroSettings.tcl
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_sta.SDC
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_Synth.log
rs232_完整版/ProjectOutputs/rs232_v2/FPGA_Project2_UserConstraints.TCL
rs232_完整版/ProjectOutputs/rs232_v2/FRQCNT2.VQM
rs232_完整版/ProjectOutputs/rs232_v2/J8S_8B.VHD
rs232_完整版/ProjectOutputs/rs232_v2/LPM_COMPARE_32_32.dep
rs232_完整版/ProjectOutputs/rs232_v2/LPM_COMPARE_32_32.vhd
rs232_完整版/ProjectOutputs/rs232_v2/Sheet2.VHD
rs232_完整版/ProjectOutputs/rs232_v2/Status Report.Txt
rs232_完整版/ProjectOutputs/rs232_v2/_blf/baud_body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/baud_header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_10__body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_10__header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_16__body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_16__header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_1__body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_1__header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_8__body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_8__header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DRNOOUT_32__body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_DRNOOUT_32__header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_TAPCONTROLLER_body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1DIGITAL_IO_TAPCONTROLLER_header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1_body.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u1_header.blf
rs232_完整版/ProjectOutputs/rs232_v2/_blf/configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16
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