docs/app64.pdf
docs/cardbus.htm
docs/compact.htm
docs/design.pdf
docs/implementation.pdf
docs/README
docs/relnote64.htm
README
verilog/example/func_sim/modelsim.do
verilog/example/func_sim/ping_tb.f
verilog/example/func_sim/README
verilog/example/func_sim/signalscan.do
verilog/example/post_sim/modelsim.do
verilog/example/post_sim/ping_tb.f
verilog/example/post_sim/README
verilog/example/post_sim/signalscan.do
verilog/example/README
verilog/example/source/busrecord.v
verilog/example/source/cfg_ping.v
verilog/example/source/dumb_arbiter.v
verilog/example/source/dumb_targ32.v
verilog/example/source/dumb_targ64.v
verilog/example/source/glbl.v
verilog/example/source/pcim_top.v
verilog/example/source/ping.v
verilog/example/source/ping_tb.v
verilog/example/source/README
verilog/example/source/stimulus.v
verilog/example/synthesis/.synopsys_dc.setup
verilog/example/synthesis/leonardo.tcl
verilog/example/synthesis/README
verilog/example/synthesis/run_xst.bat
verilog/example/synthesis/run_xst.cmd
verilog/example/synthesis/run_xst.csh
verilog/example/synthesis/run_xst.prj
verilog/example/synthesis/synopsys.dc
verilog/example/synthesis/WORK/.dummy
verilog/example/xilinx/README
verilog/example/xilinx/run_xilinx
verilog/example/xilinx/run_xilinx.bat
verilog/README
verilog/src/guide/2s150fg456_64_66.ncd
verilog/src/guide/2s200fg456_64_66.ncd
verilog/src/guide/2s300efg456_64_66.ncd
verilog/src/guide/2v1000fg456_64_66.ncd
verilog/src/guide/README
verilog/src/guide/v1000efg680_64_66.ncd
verilog/src/guide/v1000fg680_64_66.ncd
verilog/src/guide/v300bg432_64_66.ncd
verilog/src/guide/v300ebg432_64_66.ncd
verilog/src/README
verilog/src/ucf/2s100efg456_64_33.ucf
verilog/src/ucf/2s100fg456_64_33.ucf
verilog/src/ucf/2s150efg456_64_33.ucf
verilog/src/ucf/2s150fg456_64_33.ucf
verilog/src/ucf/2s150fg456_64_66.ucf
verilog/src/ucf/2s200efg456_64_33.ucf
verilog/src/ucf/2s200fg456_64_33.ucf
verilog/src/ucf/2s200fg456_64_66.ucf
verilog/src/ucf/2s300efg456_64_33.ucf
verilog/src/ucf/2s300efg456_64_66.ucf
verilog/src/ucf/2v1000fg456_64_33.ucf
verilog/src/ucf/2v1000fg456_64_66.ucf
verilog/src/ucf/2vp7ff672_64_33.ucf
verilog/src/ucf/2vp7ff672_64_66.ucf
verilog/src/ucf/3s1000fg456_64_33.ucf
verilog/src/ucf/README
verilog/src/ucf/v1000efg680_64_33.ucf
verilog/src/ucf/v1000efg680_64_66.ucf
verilog/src/ucf/v1000fg680_64_33.ucf
verilog/src/ucf/v1000fg680_64_66.ucf
verilog/src/ucf/v100ebg352_64_33.ucf
verilog/src/ucf/v300bg432_64_33.ucf
verilog/src/ucf/v300bg432_64_66.ucf
verilog/src/ucf/v300ebg432_64_33.ucf
verilog/src/ucf/v300ebg432_64_66.ucf
verilog/src/wrap/pcim_lc_33_3_s.v
verilog/src/wrap/pcim_lc_33_5_s.v
verilog/src/wrap/pcim_lc_66_3_d.v
verilog/src/wrap/pcim_lc_66_3_s.v
verilog/src/wrap/README
verilog/src/xpci/cfg.v
verilog/src/xpci/pcim_lc.v
verilog/src/xpci/pcim_top.v
verilog/src/xpci/pci_lc_i.ngo
verilog/src/xpci/pci_lc_i.v
verilog/src/xpci/README
verilog/src/xpci/userapp.v
vhdl/example/func_sim/.synopsys_vss.setup
vhdl/example/func_sim/analyze_ping
vhdl/example/func_sim/modelsim.do
vhdl/example/func_sim/ping.files
vhdl/example/func_sim/ping.include
vhdl/example/func_sim/ping.traces
vhdl/example/func_sim/ping.wfc
vhdl/example/func_sim/README
vhdl/example/func_sim/run_ping
vhdl/example/post_sim/.synopsys_vss.setup
vhdl/example/post_sim/analyze_ping
vhdl/example/post_sim/modelsim.do
vhdl/example/post_sim/ping.files
vhdl/example/post_sim/ping.include
vhdl/example/post_sim/ping.traces
vhdl/example/post_sim/ping.wfc
vhdl/example/post_sim/README
vhdl/example/post_sim/run_ping
vhdl/example/README
vhdl/example/source/busrecord.vhd
vhdl/example/source/cfg_ping.vhd
vhdl/example/source/dumb_arbiter.vhd
vhdl/example/source/dumb_targ32.vhd
vhdl/example/source/dumb_targ64.vhd
vhdl/example/source/pcim_top.vhd
vhdl/example/source/ping.vhd
vhdl/example/source/ping_tb.vhd
vhdl/example/source/README
vhdl/example/source/stimulus.vhd
vhdl/example/synthesis/.synopsys_dc.setup
vhdl/example/synthesis/leonardo.tcl
vhdl/example/synthesis/README
vhdl/example/synthesis/run_xst.bat
vhdl/example/synthesis/run_xst.cmd
vhdl/example/synthesis/run_xst.csh
vhdl/example/synthesis/run_xst.prj
vhdl/example/synthesis/synopsys.dc
vhdl/example/synthesis/WORK/.dummy
vhdl/example/xilinx/README
vhdl/example/xilinx/run_xilinx
vhdl/example/xilinx/run_xilinx.bat
vhdl/README
vhdl/src/guide/2s150fg456_64_66.ncd
vhdl/src/guide/2s200fg456_64_66.ncd
vhdl/src/guide/2s300efg456_64_66.ncd
vhdl/src/guide/2v1000fg456_64_66.ncd
vhdl/src/guide/README
vhdl/src/guide/v1000efg680_64_66.ncd
vhdl/src/guide/v1000fg680_64_66.ncd
vhdl/src/guide/v300bg432_64_66.ncd
vhdl/src/guide/v300ebg432_64_66.ncd
vhdl/src/README
vhdl/src/ucf/2s100efg456_64_33.ucf
vhdl/src/ucf/2s100fg456_64_33.ucf
vhdl/src/ucf/2s150efg456_64_33.ucf
vhdl/src/ucf/2s150fg456_64_33.ucf
vhdl/src/ucf/2s150fg456_64_66.ucf
vhdl/src/ucf/2s200efg456_64_33.ucf
vhdl/src/ucf/2s200fg456_64_33.ucf
vhdl/src/ucf/2s200fg456_64_66.ucf
vhdl/src/ucf/2s300efg456_64_33.ucf
vhdl/src/ucf/2s300efg456_64_66.ucf
vhdl/src/ucf/2v1000fg456_64_33.ucf
vhdl/src/ucf/2v1000fg456_64_66.ucf
vhdl/src/ucf/2vp7ff672_64_33.ucf
vhdl/src/ucf/2vp7ff672_64_66.ucf
vhdl/src/ucf/3s1000fg456_64_33.ucf
vhd