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文件名称:sdramcontroller.rar

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-09-04
  • 文件大小：
    2.28mb
  • 已下载：
    0次
  • 提 供 者：
    文***
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

最完整的SDRAM控制IP核，包括源代码，仿真文件，以及IP核描述文件，包你用得上,SDRAM control of the most complete IP core, including source code, simulation, as well as IP core descr iption files, it can be helpful
(系统自动生成,下载前可以参看下载内容)

下载文件列表

sdr sdram controller/sdr_sdram.pdf
sdr sdram controller/vhdl/synthesis/synplicity/readme.txt
sdr sdram controller/vhdl/synthesis/synplicity/sdr_sdram.prj
sdr sdram controller/vhdl/synthesis/synplicity/sdr_sdram.vqm
sdr sdram controller/vhdl/source/Command.vhd
sdr sdram controller/vhdl/source/control_interface.vhd
sdr sdram controller/vhdl/source/pll1.vhd
sdr sdram controller/vhdl/source/sdr_data_path.vhd
sdr sdram controller/vhdl/source/sdr_sdram.vhd
sdr sdram controller/vhdl/simulation/APEX20KE_MF.VHD
sdr sdram controller/vhdl/simulation/Command.vhd
sdr sdram controller/vhdl/simulation/control_interface.vhd
sdr sdram controller/vhdl/simulation/io_utils.vhd
sdr sdram controller/vhdl/simulation/lpm_pack.vhd
sdr sdram controller/vhdl/simulation/modelsim.ini
sdr sdram controller/vhdl/simulation/mt48lc8m16a2.vhd
sdr sdram controller/vhdl/simulation/mt48lc8m16a2.vhd.bak
sdr sdram controller/vhdl/simulation/mti_pkg.vhd
sdr sdram controller/vhdl/simulation/pll1.vhd
sdr sdram controller/vhdl/simulation/pll1.vhd.bak
sdr sdram controller/vhdl/simulation/readme.txt
sdr sdram controller/vhdl/simulation/sdram.mpf
sdr sdram controller/vhdl/simulation/sdr_data_path.vhd
sdr sdram controller/vhdl/simulation/sdr_sdram.vhd
sdr sdram controller/vhdl/simulation/sdr_sdram_tb.vhd
sdr sdram controller/vhdl/simulation/sdr_sdram_tb.vhd.bak
sdr sdram controller/vhdl/simulation/stdlogar.vhd
sdr sdram controller/vhdl/simulation/tcl_stacktrace.txt
sdr sdram controller/vhdl/simulation/transcript
sdr sdram controller/vhdl/simulation/util1164.vhd
sdr sdram controller/vhdl/simulation/work/_info
sdr sdram controller/vhdl/simulation/work/util_1164/body.dat
sdr sdram controller/vhdl/simulation/work/util_1164/body.psm
sdr sdram controller/vhdl/simulation/work/util_1164/_primary.dat
sdr sdram controller/vhdl/simulation/work/util_1164/_vhdl.psm
sdr sdram controller/vhdl/simulation/work/std_logic_arith/body.dat
sdr sdram controller/vhdl/simulation/work/std_logic_arith/body.psm
sdr sdram controller/vhdl/simulation/work/std_logic_arith/_primary.dat
sdr sdram controller/vhdl/simulation/work/std_logic_arith/_vhdl.psm
sdr sdram controller/vhdl/simulation/work/sdr_sdram_tb/rtl.dat
sdr sdram controller/vhdl/simulation/work/sdr_sdram_tb/rtl.psm
sdr sdram controller/vhdl/simulation/work/sdr_sdram_tb/_primary.dat
sdr sdram controller/vhdl/simulation/work/sdr_sdram/rtl.dat
sdr sdram controller/vhdl/simulation/work/sdr_sdram/rtl.psm
sdr sdram controller/vhdl/simulation/work/sdr_sdram/_primary.dat
sdr sdram controller/vhdl/simulation/work/sdr_data_path/rtl.dat
sdr sdram controller/vhdl/simulation/work/sdr_data_path/rtl.psm
sdr sdram controller/vhdl/simulation/work/sdr_data_path/_primary.dat
sdr sdram controller/vhdl/simulation/work/pll1/syn.dat
sdr sdram controller/vhdl/simulation/work/pll1/syn.psm
sdr sdram controller/vhdl/simulation/work/pll1/_primary.dat
sdr sdram controller/vhdl/simulation/work/mti_pkg/body.dat
sdr sdram controller/vhdl/simulation/work/mti_pkg/body.psm
sdr sdram controller/vhdl/simulation/work/mti_pkg/_primary.dat
sdr sdram controller/vhdl/simulation/work/mti_pkg/_vhdl.psm
sdr sdram controller/vhdl/simulation/work/mt48lc8m16a2/behave.dat
sdr sdram controller/vhdl/simulation/work/mt48lc8m16a2/behave.psm
sdr sdram controller/vhdl/simulation/work/mt48lc8m16a2/_primary.dat
sdr sdram controller/vhdl/simulation/work/io_utils/body.dat
sdr sdram controller/vhdl/simulation/work/io_utils/body.psm
sdr sdram controller/vhdl/simulation/work/io_utils/_primary.dat
sdr sdram controller/vhdl/simulation/work/io_utils/_vhdl.psm
sdr sdram controller/vhdl/simulation/work/control_interface/rtl.dat
sdr sdram controller/vhdl/simulation/work/control_interface/rtl.psm
sdr sdram controller/vhdl/simulation/work/control_interface/_primary.dat
sdr sdram controller/vhdl/simulation/work/command/rtl.dat
sdr sdram controller/vhdl/simulation/work/command/rtl.psm
sdr sdram controller/vhdl/simulation/work/command/_primary.dat
sdr sdram controller/vhdl/simulation/work/altlvds_tx/behavior.dat
sdr sdram controller/vhdl/simulation/work/altlvds_tx/behavior.psm
sdr sdram controller/vhdl/simulation/work/altlvds_tx/_primary.dat
sdr sdram controller/vhdl/simulation/work/altlvds_rx/behavior.dat
sdr sdram controller/vhdl/simulation/work/altlvds_rx/behavior.psm
sdr sdram controller/vhdl/simulation/work/altlvds_rx/_primary.dat
sdr sdram controller/vhdl/simulation/work/altclklock/behavior.dat
sdr sdram controller/vhdl/simulation/work/altclklock/behavior.psm
sdr sdram controller/vhdl/simulation/work/altclklock/_primary.dat
sdr sdram controller/vhdl/simulation/work/altcam/behave.dat
sdr sdram controller/vhdl/simulation/work/altcam/behave.psm
sdr sdram controller/vhdl/simulation/work/altcam/_primary.dat
sdr sdram controller/vhdl/route/pll1.vhd
sdr sdram controller/vhdl/route/sdr_sdram.csf
sdr sdram controller/vhdl/route/sdr_sdram.esf
sdr sdram controller/vhdl/route/sdr_sdram.vqm
sdr sdram controller/vhdl/model/io_utils.vhd
sdr sdram controller/vhdl/model/mt48lc8m16a2.vhd
sdr sdram controller/vhdl/model/mt48lc8m16a2.zip
sdr sdram controller/vhdl/model/mti_pkg.vhd
sdr sdram controller/vhdl/model/stdlogar.vhd
sdr

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