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文件名称:open_cores_VGAcore

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2012-10-28
  • 文件大小：
    2.05mb
  • 已下载：
    0次
  • 提 供 者：
    张***
  • 相关连接：
    无
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老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core grasp of bus protocol
(系统自动生成,下载前可以参看下载内容)

下载文件列表

open_cores/vga_core.pdf
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/bench/verilog/wb_slv_model.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/bench/verilog/wb_model_defines.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/bench/verilog/test_bench_top.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/bench/verilog/tests.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/bench/verilog/wb_mast_model.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/bench/verilog/wb_b3_check.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/software/include/oc_vga_lcd.h
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/sim/rtl_sim/bin/Makefile
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/syn/bin/comp.dc
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/syn/bin/design_spec.dc
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/syn/bin/read.dc
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/syn/bin/lib_spec.dc
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/doc/vga_core.pdf
open_cores/vga_lcd_latest/vga_lcd/tags/rel_19/doc/src/vga_core_enh.doc
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/bench/verilog/wb_slv_model.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/bench/verilog/wb_model_defines.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/bench/verilog/test_bench_top.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/bench/verilog/tests.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/bench/verilog/sync_check.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/bench/verilog/wb_mast_model.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/software/include/oc_vga_lcd.h
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/sim/rtl_sim/bin/Makefile
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/syn/bin/comp.dc
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/syn/bin/design_spec.dc
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/syn/bin/read.dc
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/syn/bin/lib_spec.dc
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/counter.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/fifo_dc.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/vtim.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/vga_and_clut_tstbench.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/vga_and_clut.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/fifo.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/vga.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/csm_pb.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/colproc.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/tgen.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/wb_master.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/dpm.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/wb_slave.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/vhdl/pgen.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/generic_dpram.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/timescale.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_fifo_dc.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/generic_spram.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_colproc.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_fifo.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_enh_top.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_cur_cregs.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_curproc.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/ro_cnt.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_wb_master.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_defines.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_pgen.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/ud_cnt.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_vtim.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_wb_slave.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_csm_pb.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/rtl/verilog/vga_tgen.v
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/doc/vga_core.pdf
open_cores/vga_lcd_latest/vga_lcd/tags/rel_1/doc/src/vga_core_enh.doc
open_cores/vga_lcd_latest/vga_lcd/tags/beta/counter.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/beta/vga_wave.do
open_cores/vga_lcd_latest/vga_lcd/tags/beta/fifo_dc.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/beta/vga_8bpp_pc_sim.do
open_cores/vga_lcd_latest/vga_lcd/tags/beta/vtim.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/beta/fifo.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/beta/vga_16bpp_sim.do
open_cores/vga_lcd_latest/vga_lcd/tags/beta/vga_24bpp_sim.do
open_cores/vga_lcd_latest/vga_lcd/tags/beta/vga.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/beta/colproc.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/beta/tgen.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/beta/wb_master.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/beta/dpm.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/beta/wb_slave.vhd
open_cores/vga_lcd_latest/vga_lcd/tags/beta/vga_8bpp_gray_sim.do
open_cores/vga_lcd_la

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