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- ddr_top This VHDL or Verilog source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user s responsibility to verify their design for // consistency and functionality through the use of formal // verification methods. Lattice Semiconductor provides no warranty // regarding the use or functionality of this code.
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文件名称:24C64(msp430)
介绍说明－－下载内容来自于网络，使用问题请自行百度
MSP430单片机中，对于存储器at24c64的读写操作程序-MSP430 MCU for memory reads and writes procedures at24c64
(系统自动生成,下载前可以参看下载内容)
下载文件列表
24C64(msp430)/24c16.dep
24C64(msp430)/24c16.ewd
24C64(msp430)/24c16.ewp
24C64(msp430)/24c64.eww
24C64(msp430)/at64_i2c.c
24C64(msp430)/at64_i2c.h
24C64(msp430)/main.c
24C64(msp430)/usart.c
24C64(msp430)/usart.h
24C64(msp430)/Debug/Exe/24c16.d43
24C64(msp430)/Debug/Obj/24c16.pbd
24C64(msp430)/Debug/Obj/at64_i2c.r43
24C64(msp430)/Debug/Obj/main.r43
24C64(msp430)/Debug/Obj/usart.r43
24C64(msp430)/settings/24c16.cspy.bat
24C64(msp430)/settings/24c16.dbgdt
24C64(msp430)/settings/24c16.dni
24C64(msp430)/settings/24c64.wsdt
24C64(msp430)/Debug/Exe
24C64(msp430)/Debug/List
24C64(msp430)/Debug/Obj
24C64(msp430)/Debug
24C64(msp430)/settings
24C64(msp430)
24C64(msp430)/24c16.ewd
24C64(msp430)/24c16.ewp
24C64(msp430)/24c64.eww
24C64(msp430)/at64_i2c.c
24C64(msp430)/at64_i2c.h
24C64(msp430)/main.c
24C64(msp430)/usart.c
24C64(msp430)/usart.h
24C64(msp430)/Debug/Exe/24c16.d43
24C64(msp430)/Debug/Obj/24c16.pbd
24C64(msp430)/Debug/Obj/at64_i2c.r43
24C64(msp430)/Debug/Obj/main.r43
24C64(msp430)/Debug/Obj/usart.r43
24C64(msp430)/settings/24c16.cspy.bat
24C64(msp430)/settings/24c16.dbgdt
24C64(msp430)/settings/24c16.dni
24C64(msp430)/settings/24c64.wsdt
24C64(msp430)/Debug/Exe
24C64(msp430)/Debug/List
24C64(msp430)/Debug/Obj
24C64(msp430)/Debug
24C64(msp430)/settings
24C64(msp430)
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