test
test/ise
test/ise/test.npl
test/ise/__projnav
test/ise/__projnav/coregen.rsp
test/ise/__projnav/runXst_tcl.rsp
test/ise/__projnav/test_flowplus.gfl
test/ise/__projnav/test.gfl
test/ise/__projnav/fpga.xst
test/ise/fpga.ngr
test/ise/fpga.ngc
test/ise/test.dhp
test/ise/coregen.log
test/ise/coregen.prj
test/ise/__projnav.log
test/ise/automake.log
test/ise/fpga.prj
test/ise/fpga.cmd_log
test/ise/fpga.syr
test/ise/xst
test/ise/xst/work
test/ise/xst/work/vlg22
test/ise/xst/work/vlg22/fpga.bin
test/ise/xst/work/hdllib.ref
test/ise/fpga.stx
test/ise/fpga_vhdl.prj
test/ise/fpga.lso
test/modelsim
test/modelsim/work
test/modelsim/work/_info
test/modelsim/work/fpga
test/modelsim/work/fpga/_primary.vhd
test/modelsim/work/fpga/verilog.asm
test/modelsim/work/fpga/_primary.dat
test/modelsim/work/@v51
test/modelsim/work/@v51/_primary.vhd
test/modelsim/work/@v51/verilog.asm
test/modelsim/work/@v51/_primary.dat
test/modelsim/work/top
test/modelsim/work/top/_primary.vhd
test/modelsim/work/top/verilog.asm
test/modelsim/work/top/_primary.dat
test/modelsim/work/mt48lc1m16a1
test/modelsim/work/mt48lc1m16a1/_primary.vhd
test/modelsim/work/mt48lc1m16a1/verilog.asm
test/modelsim/work/mt48lc1m16a1/_primary.dat
test/modelsim/test.cr.mti
test/modelsim/wave2.do
test/modelsim/test.mpf
test/modelsim/wave.do
test/modelsim/vsim.wlf
test/src
test/src/top.v
test/src/V51.v
test/src/fpga.v
test/src/global.h
test/src/mt48lc1m16a1-8a.v
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