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文件名称:100Examples[1`20]
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- 上传时间：2012-11-16
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文件大小：49.46kb
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VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是1-20个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC published examples here is 1-20 months
(系统自动生成,下载前可以参看下载内容)
下载文件列表
20_test_159/20_test_159.vhd
1_ADDER/1_ADDER.VHD
1_ADDER/README.TXT
2_ADDER/2_ADDER.VHD
2_ADDER/README.TXT
3_MUL/3_MUL.VHD
3_MUL/README.TXT
4_COMP/4_COMP.VHD
4_COMP/README.TXT
5_MUX2/5_MUX2.VHD
5_MUX2/README.TXT
6_REG/6_REG.VHD
6_REG/README.TXT
7_shiftreg/7_MVL7_functions.vhd
7_shiftreg/7_shiftreg.vhd
7_shiftreg/7_synthesis_types.vhd
7_shiftreg/7_test_vector.vhd
7_shiftreg/7_TYPES.VHD
7_shiftreg/README.TXT
8_BITPKG/8_BITPKG.VHD
8_BITPKG/8_bit_rtl_lib.vhd
8_BITPKG/README.TXT
9_MVL7_TYPES/9_MVL7_types.vhd
9_MVL7_TYPES/README.TXT
10_function/10_bit_to_int.vhd
10_function/README.TXT
11_wiredor/11_wiredor.vhd
11_wiredor/README.TXT
12_convert/12_convert.vhd
12_convert/README.TXT
13_SHL/13_SHL.VHD
13_SHL/README.TXT
14_MVL7_functions/14_MVL7_functions.vhd
14_MVL7_functions/README.TXT
15_MUX41/15_MUX41.VHD
15_MUX41/15_MVL7_functions.vhd
15_MUX41/15_MVL7_syn_types.vhd
15_MUX41/15_test_vectors_mux41.vhd
15_MUX41/15_TYPES.VHD
15_MUX41/README.TXT
16_MUX/16_multiple_mux.vhd
16_MUX/16_MVL7_functions.vhd
16_MUX/16_test_vectors.vhd
16_MUX/16_TYPES.VHD
16_MUX/README.TXT
16_MUX/TYPES.VHD
17_parity/17_parity.vhd
17_parity/17_test_bench.vhd
17_parity/README.TXT
18_LIB/18_tech_lib.vhd
18_LIB/18_test_lib.vhd
18_LIB/README.TXT
19_test_194/19_test_194.vhd
20_test_159
1_ADDER
2_ADDER
3_MUL
4_COMP
5_MUX2
6_REG
7_shiftreg
8_BITPKG
9_MVL7_TYPES
10_function
11_wiredor
12_convert
13_SHL
14_MVL7_functions
15_MUX41
16_MUX
17_parity
18_LIB
19_test_194
1_ADDER/1_ADDER.VHD
1_ADDER/README.TXT
2_ADDER/2_ADDER.VHD
2_ADDER/README.TXT
3_MUL/3_MUL.VHD
3_MUL/README.TXT
4_COMP/4_COMP.VHD
4_COMP/README.TXT
5_MUX2/5_MUX2.VHD
5_MUX2/README.TXT
6_REG/6_REG.VHD
6_REG/README.TXT
7_shiftreg/7_MVL7_functions.vhd
7_shiftreg/7_shiftreg.vhd
7_shiftreg/7_synthesis_types.vhd
7_shiftreg/7_test_vector.vhd
7_shiftreg/7_TYPES.VHD
7_shiftreg/README.TXT
8_BITPKG/8_BITPKG.VHD
8_BITPKG/8_bit_rtl_lib.vhd
8_BITPKG/README.TXT
9_MVL7_TYPES/9_MVL7_types.vhd
9_MVL7_TYPES/README.TXT
10_function/10_bit_to_int.vhd
10_function/README.TXT
11_wiredor/11_wiredor.vhd
11_wiredor/README.TXT
12_convert/12_convert.vhd
12_convert/README.TXT
13_SHL/13_SHL.VHD
13_SHL/README.TXT
14_MVL7_functions/14_MVL7_functions.vhd
14_MVL7_functions/README.TXT
15_MUX41/15_MUX41.VHD
15_MUX41/15_MVL7_functions.vhd
15_MUX41/15_MVL7_syn_types.vhd
15_MUX41/15_test_vectors_mux41.vhd
15_MUX41/15_TYPES.VHD
15_MUX41/README.TXT
16_MUX/16_multiple_mux.vhd
16_MUX/16_MVL7_functions.vhd
16_MUX/16_test_vectors.vhd
16_MUX/16_TYPES.VHD
16_MUX/README.TXT
16_MUX/TYPES.VHD
17_parity/17_parity.vhd
17_parity/17_test_bench.vhd
17_parity/README.TXT
18_LIB/18_tech_lib.vhd
18_LIB/18_test_lib.vhd
18_LIB/README.TXT
19_test_194/19_test_194.vhd
20_test_159
1_ADDER
2_ADDER
3_MUL
4_COMP
5_MUX2
6_REG
7_shiftreg
8_BITPKG
9_MVL7_TYPES
10_function
11_wiredor
12_convert
13_SHL
14_MVL7_functions
15_MUX41
16_MUX
17_parity
18_LIB
19_test_194
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