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文件名称:lab1

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    2012-11-16
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基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程:实验1简单的硬件设计实验-Xilinx-XUPV2P-based development platform for embedded system routine experiments: Experiment 1 a simple hardware design experiment
相关搜索: xupv2p lab1

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下载文件列表

lab1/data/system.ucf
lab1/etc/download.cmd
lab1/etc/fast_runtime.opt
lab1/hdl/dcm_0_wrapper.vhd
lab1/hdl/elaborate/plb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/plb_bram_if_cntlr_1_bram_elaborate.vhd
lab1/hdl/jtagppc_0_wrapper.vhd
lab1/hdl/opb_wrapper.vhd
lab1/hdl/plb2opb_wrapper.vhd
lab1/hdl/plb_bram_if_cntlr_1_bram_wrapper.vhd
lab1/hdl/plb_bram_if_cntlr_1_wrapper.vhd
lab1/hdl/plb_wrapper.vhd
lab1/hdl/ppc405_0_wrapper.vhd
lab1/hdl/ppc405_1_wrapper.vhd
lab1/hdl/reset_block_wrapper.vhd
lab1/hdl/rs232_uart_1_wrapper.vhd
lab1/hdl/system.vhd
lab1/implementation/cache/cache.cat
lab1/implementation/cache/dcm_0_wrapper.ngc
lab1/implementation/cache/jtagppc_0_wrapper.ngc
lab1/implementation/cache/opb_wrapper.ngc
lab1/implementation/cache/plb2opb_wrapper.ngc
lab1/implementation/cache/plb_bram_if_cntlr_1_bram_wrapper.ngc
lab1/implementation/cache/plb_bram_if_cntlr_1_wrapper.ngc
lab1/implementation/cache/plb_wrapper.ngc
lab1/implementation/cache/ppc405_0_wrapper.ngc
lab1/implementation/cache/ppc405_1_wrapper.ngc
lab1/implementation/cache/reset_block_wrapper.ngc
lab1/implementation/cache/rs232_uart_1_wrapper.ngc
lab1/implementation/dcm_0_wrapper/dcm_0_wrapper.ngc
lab1/implementation/dcm_0_wrapper.ngc
lab1/implementation/jtagppc_0_wrapper/jtagppc_0_wrapper.ngc
lab1/implementation/jtagppc_0_wrapper.ngc
lab1/implementation/opb_wrapper/opb_wrapper.ngc
lab1/implementation/opb_wrapper.ngc
lab1/implementation/plb2opb_wrapper/plb2opb_wrapper.ngc
lab1/implementation/plb2opb_wrapper.ngc
lab1/implementation/plb_bram_if_cntlr_1_bram_wrapper/plb_bram_if_cntlr_1_bram_wrapper.ngc
lab1/implementation/plb_bram_if_cntlr_1_bram_wrapper.ngc
lab1/implementation/plb_bram_if_cntlr_1_wrapper/plb_bram_if_cntlr_1_wrapper.ngc
lab1/implementation/plb_bram_if_cntlr_1_wrapper.ngc
lab1/implementation/plb_wrapper/plb_wrapper.ngc
lab1/implementation/plb_wrapper.ngc
lab1/implementation/ppc405_0_wrapper/ppc405_0_wrapper.ngc
lab1/implementation/ppc405_0_wrapper.ngc
lab1/implementation/ppc405_1_wrapper/ppc405_1_wrapper.ngc
lab1/implementation/ppc405_1_wrapper.ngc
lab1/implementation/reset_block_wrapper/reset_block_wrapper.ngc
lab1/implementation/reset_block_wrapper.ngc
lab1/implementation/rs232_uart_1_wrapper/rs232_uart_1_wrapper.ngc
lab1/implementation/rs232_uart_1_wrapper.ngc
lab1/implementation/system.bmm
lab1/implementation/system.ngc
lab1/platgen.log
lab1/platgen.opt
lab1/synthesis/dcm_0_wrapper.lso
lab1/synthesis/dcm_0_wrapper_xst.prj
lab1/synthesis/dcm_0_wrapper_xst.scr
lab1/synthesis/dcm_0_wrapper_xst.srp
lab1/synthesis/jtagppc_0_wrapper.lso
lab1/synthesis/jtagppc_0_wrapper_xst.prj
lab1/synthesis/jtagppc_0_wrapper_xst.scr
lab1/synthesis/jtagppc_0_wrapper_xst.srp
lab1/synthesis/opb_wrapper.lso
lab1/synthesis/opb_wrapper_xst.prj
lab1/synthesis/opb_wrapper_xst.scr
lab1/synthesis/opb_wrapper_xst.srp
lab1/synthesis/plb2opb_wrapper.lso
lab1/synthesis/plb2opb_wrapper_xst.prj
lab1/synthesis/plb2opb_wrapper_xst.scr
lab1/synthesis/plb2opb_wrapper_xst.srp
lab1/synthesis/plb_bram_if_cntlr_1_bram_wrapper.lso
lab1/synthesis/plb_bram_if_cntlr_1_bram_wrapper_xst.prj
lab1/synthesis/plb_bram_if_cntlr_1_bram_wrapper_xst.scr
lab1/synthesis/plb_bram_if_cntlr_1_bram_wrapper_xst.srp
lab1/synthesis/plb_bram_if_cntlr_1_wrapper.lso
lab1/synthesis/plb_bram_if_cntlr_1_wrapper_xst.prj
lab1/synthesis/plb_bram_if_cntlr_1_wrapper_xst.scr
lab1/synthesis/plb_bram_if_cntlr_1_wrapper_xst.srp
lab1/synthesis/plb_wrapper.lso
lab1/synthesis/plb_wrapper_xst.prj
lab1/synthesis/plb_wrapper_xst.scr
lab1/synthesis/plb_wrapper_xst.srp
lab1/synthesis/ppc405_0_wrapper.lso
lab1/synthesis/ppc405_0_wrapper_xst.prj
lab1/synthesis/ppc405_0_wrapper_xst.scr
lab1/synthesis/ppc405_0_wrapper_xst.srp
lab1/synthesis/ppc405_1_wrapper.lso
lab1/synthesis/ppc405_1_wrapper_xst.prj
lab1/synthesis/ppc405_1_wrapper_xst.scr
lab1/synthesis/ppc405_1_wrapper_xst.srp
lab1/synthesis/reset_block_wrapper.lso
lab1/synthesis/reset_block_wrapper_xst.prj
lab1/synthesis/reset_block_wrapper_xst.scr
lab1/synthesis/reset_block_wrapper_xst.srp
lab1/synthesis/rs232_uart_1_wrapper.lso
lab1/synthesis/rs232_uart_1_wrapper_xst.prj
lab1/synthesis/rs232_uart_1_wrapper_xst.scr
lab1/synthesis/rs232_uart_1_wrapper_xst.srp
lab1/synthesis/synthesis.sh
lab1/synthesis/system.lso
lab1/synthesis/system_xst.prj
lab1/synthesis/system_xst.scr
lab1/synthesis/system_xst.srp
lab1/system.bsb
lab1/system.gui
lab1/system.log
lab1/system.make
lab1/system.mhs
lab1/system.mss
lab1/system.xmp
lab1/system_incl.make
lab1/TestApp_Memory/src/TestApp_Memory.c
lab1/TestApp_Memory/src/TestApp_Memory_LinkScr.ld
lab1/TestApp_Peripheral/src/TestApp_Peripheral.c
lab1/TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld
lab1/__xps/bitinit.opt
lab1/__xps/libgen.opt
lab1/__xps/platgen.opt
lab1/__xps/simgen.opt
lab1/__xps/testapp_memory_compiler.opt
lab1/__xps/testapp_peripheral_compiler.opt
lab1/__xps/vpgen.opt
lab1/__xps/xpsxflow.opt
lab1/hdl/elaborate/plb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl
lab1/hdl/elaborate/plb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl
lab1/hdl/elaborate/plb_bram_if_cntlr_1_bram_elaborate_v1_00_a
lab1/hdl/elaborate
lab1/implementation/cache
lab1/imple

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