利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点-In addition to the completion of the use of a chip clock source, buttons, speakers and monitors (digital tube) all the figures outside the circuit functions. All digital logic functions are used in the CPLD devices VHDL language. This design has a small size, short design cycle (the design process to achieve timing simulation), debugging convenient, low failure rate, modify the characteristics of easy upgrade