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文件名称:adc
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- 上传时间：2012-11-16
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This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assuming a 30Mhz XCLKIN). The
clock divider in the ADC is not used so that the ADC will see the 25Mhz on the HSPCLK. Interrupts are enabled and the EVA is setup to generate a periodic ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2.
clock divider in the ADC is not used so that the ADC will see the 25Mhz on the HSPCLK. Interrupts are enabled and the EVA is setup to generate a periodic ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Example_281xAdcSoc.c
Example_281xAdcSoc.gel
Example_281xAdcSoc.pjt
Example_281xAdcSoc.gel
Example_281xAdcSoc.pjt
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