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文件名称:pinlvji

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  • 上传时间:
    2012-11-16
  • 文件大小:
    10.34mb
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    0次
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    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

用4位十进制计数器对用户输入时钟信号进行计数,计数间隔为1秒钟。计数满1秒钟后将计数值(即频率值)所存到4位寄存器中显示,并将计数器清0,在进行下一次计数。

频率计由三种模块组成:testctl为控制模块,由1Hz其准产生rst_cnt,load,cnt_en信号;cnt10为带清0及计数允许的十进制计数器;reg4b为四位寄存器。

-With four decimal counter input clock signal to the user to count, count one second interval. 1 seconds after the full count of values (that is, the frequency value) stored in the register to display 4, and Counter-ching 0, the time of the next count.

Frequency of three modules: testctl for the control module, the alignment of 1Hz generated by rst_cnt, load, cnt_en signal cnt10 with clearance for the count 0 and the decimal counter permit reg4b register for the four.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

lianxi5/bj/alt_max2.vo
lianxi5/bj/frequen_cout(1).cnf
lianxi5/bj/frequen_cout(2).cnf
lianxi5/bj/frequen_cout.acf
lianxi5/bj/frequen_cout.cnf
lianxi5/bj/frequen_cout.edf
lianxi5/bj/frequen_cout.fit
lianxi5/bj/frequen_cout.hex
lianxi5/bj/frequen_cout.hif
lianxi5/bj/frequen_cout.mmf
lianxi5/bj/frequen_cout.ndb
lianxi5/bj/frequen_cout.pin
lianxi5/bj/frequen_cout.pof
lianxi5/bj/frequen_cout.rpt
lianxi5/bj/frequen_cout.snf
lianxi5/bj/frequen_cout.sof
lianxi5/bj/frequen_cout.tcl
lianxi5/bj/frequen_cout.ttf
lianxi5/bj/frequen_cout.vo
lianxi5/bj/frequen_cout.xdb
lianxi5/bj/leospec.his
lianxi5/hfz/123.cr.mti
lianxi5/hfz/123.mpf
lianxi5/hfz/alt_max2.vo
lianxi5/hfz/frequen_cout.vo
lianxi5/hfz/frequen_top.v
lianxi5/hfz/transcript
lianxi5/hfz/vsim.wlf
lianxi5/hfz/work/@a@n@d1/verilog.asm
lianxi5/hfz/work/@a@n@d1/_primary.dat
lianxi5/hfz/work/@a@n@d1/_primary.vhd
lianxi5/hfz/work/@a@n@d10/verilog.asm
lianxi5/hfz/work/@a@n@d10/_primary.dat
lianxi5/hfz/work/@a@n@d10/_primary.vhd
lianxi5/hfz/work/@a@n@d11/verilog.asm
lianxi5/hfz/work/@a@n@d11/_primary.dat
lianxi5/hfz/work/@a@n@d11/_primary.vhd
lianxi5/hfz/work/@a@n@d12/verilog.asm
lianxi5/hfz/work/@a@n@d12/_primary.dat
lianxi5/hfz/work/@a@n@d12/_primary.vhd
lianxi5/hfz/work/@a@n@d13/verilog.asm
lianxi5/hfz/work/@a@n@d13/_primary.dat
lianxi5/hfz/work/@a@n@d13/_primary.vhd
lianxi5/hfz/work/@a@n@d14/verilog.asm
lianxi5/hfz/work/@a@n@d14/_primary.dat
lianxi5/hfz/work/@a@n@d14/_primary.vhd
lianxi5/hfz/work/@a@n@d15/verilog.asm
lianxi5/hfz/work/@a@n@d15/_primary.dat
lianxi5/hfz/work/@a@n@d15/_primary.vhd
lianxi5/hfz/work/@a@n@d16/verilog.asm
lianxi5/hfz/work/@a@n@d16/_primary.dat
lianxi5/hfz/work/@a@n@d16/_primary.vhd
lianxi5/hfz/work/@a@n@d2/verilog.asm
lianxi5/hfz/work/@a@n@d2/_primary.dat
lianxi5/hfz/work/@a@n@d2/_primary.vhd
lianxi5/hfz/work/@a@n@d3/verilog.asm
lianxi5/hfz/work/@a@n@d3/_primary.dat
lianxi5/hfz/work/@a@n@d3/_primary.vhd
lianxi5/hfz/work/@a@n@d4/verilog.asm
lianxi5/hfz/work/@a@n@d4/_primary.dat
lianxi5/hfz/work/@a@n@d4/_primary.vhd
lianxi5/hfz/work/@a@n@d5/verilog.asm
lianxi5/hfz/work/@a@n@d5/_primary.dat
lianxi5/hfz/work/@a@n@d5/_primary.vhd
lianxi5/hfz/work/@a@n@d6/verilog.asm
lianxi5/hfz/work/@a@n@d6/_primary.dat
lianxi5/hfz/work/@a@n@d6/_primary.vhd
lianxi5/hfz/work/@a@n@d7/verilog.asm
lianxi5/hfz/work/@a@n@d7/_primary.dat
lianxi5/hfz/work/@a@n@d7/_primary.vhd
lianxi5/hfz/work/@a@n@d8/verilog.asm
lianxi5/hfz/work/@a@n@d8/_primary.dat
lianxi5/hfz/work/@a@n@d8/_primary.vhd
lianxi5/hfz/work/@a@n@d9/verilog.asm
lianxi5/hfz/work/@a@n@d9/_primary.dat
lianxi5/hfz/work/@a@n@d9/_primary.vhd
lianxi5/hfz/work/@c@l@k@l@o@c@k/verilog.asm
lianxi5/hfz/work/@c@l@k@l@o@c@k/_primary.dat
lianxi5/hfz/work/@c@l@k@l@o@c@k/_primary.vhd
lianxi5/hfz/work/@d@e@l@a@y/verilog.asm
lianxi5/hfz/work/@d@e@l@a@y/_primary.dat
lianxi5/hfz/work/@d@e@l@a@y/_primary.vhd
lianxi5/hfz/work/@d@f@f/verilog.asm
lianxi5/hfz/work/@d@f@f/_primary.dat
lianxi5/hfz/work/@d@f@f/_primary.vhd
lianxi5/hfz/work/@d@f@f0_frequen_cout/verilog.asm
lianxi5/hfz/work/@d@f@f0_frequen_cout/_primary.dat
lianxi5/hfz/work/@d@f@f0_frequen_cout/_primary.vhd
lianxi5/hfz/work/@d@f@f1/verilog.asm
lianxi5/hfz/work/@d@f@f1/_primary.dat
lianxi5/hfz/work/@d@f@f1/_primary.vhd
lianxi5/hfz/work/@d@f@f1_frequen_cout/verilog.asm
lianxi5/hfz/work/@d@f@f1_frequen_cout/_primary.dat
lianxi5/hfz/work/@d@f@f1_frequen_cout/_primary.vhd
lianxi5/hfz/work/@d@f@f2_frequen_cout/verilog.asm
lianxi5/hfz/work/@d@f@f2_frequen_cout/_primary.dat
lianxi5/hfz/work/@d@f@f2_frequen_cout/_primary.vhd
lianxi5/hfz/work/@d@f@f3_frequen_cout/verilog.asm
lianxi5/hfz/work/@d@f@f3_frequen_cout/_primary.dat
lianxi5/hfz/work/@d@f@f3_frequen_cout/_primary.vhd
lianxi5/hfz/work/@d@f@f4_frequen_cout/verilog.asm
lianxi5/hfz/work/@d@f@f4_frequen_cout/_primary.dat
lianxi5/hfz/work/@d@f@f4_frequen_cout/_primary.vhd
lianxi5/hfz/work/@d@f@f5_frequen_cout/verilog.asm
lianxi5/hfz/work/@d@f@f5_frequen_cout/_primary.dat
lianxi5/hfz/work/@d@f@f5_frequen_cout/_primary.vhd
lianxi5/hfz/work/@d@f@f@e/verilog.asm
lianxi5/hfz/work/@d@f@f@e/_primary.dat
lianxi5/hfz/work/@d@f@f@e/_primary.vhd
lianxi5/hfz/work/@d@f@f@e1/verilog.asm
lianxi5/hfz/work/@d@f@f@e1/_primary.dat
lianxi5/hfz/work/@d@f@f@e1/_primary.vhd
lianxi5/hfz/work/@f@i@l@t@e@r/verilog.asm
lianxi5/hfz/work/@f@i@l@t@e@r/_primary.dat
lianxi5/hfz/work/@f@i@l@t@e@r/_primary.vhd
lianxi5/hfz/work/@f@i@l@t@e@r0_frequen_cout/verilog.asm
lianxi5/hfz/work/@f@i@l@t@e@r0_frequen_cout/_primary.dat
lianxi5/hfz/work/@f@i@l@t@e@r0_frequen_cout/_primary.vhd
lianxi5/hfz/work/@i@n@v/verilog.asm
lianxi5/hfz/work/@i@n@v/_primary.dat
lianxi5/hfz/work/@i@n@v/_primary.vhd
lianxi5/hfz/work/@l@a@t@c@h/verilog.asm
lianxi5/hfz/work/@l@a@t@c@h/_primary.dat
lianxi5/hfz/work/@l@a@t@c@h/_primary.vhd
lianxi5/hfz/work/@n@a@n@d1/verilog.asm
lianxi5/hfz/work/@n@a@n@d1/_primary.dat
lianxi5/hfz/work/@n@a@n@d1/_primary.vhd
lianxi5/hfz/work/@n@a@n@d10/verilog.asm
lianxi5/hfz/work/@n@a@n@d10/_primary.dat
lianxi5/hfz/work/@n@a@n@d10/_primary.vhd
lianxi5/hfz/work/@n@a@n@d11/verilog.asm
lianxi5/hfz/work/@n@a@n@d11/_primary.dat
lianxi5/hfz/work/@n@a@n@d11/_primary.vhd
lianxi5/hfz/work/@n@a@n@

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