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文件名称:voltage_comp_verilog

  • 所属分类：
    Windows Develop
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.56mb
  • 已下载：
    0次
  • 提 供 者：
    魏****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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实现对8通道模拟数据的高速采集，精度高，采用时分复用方法，避免的数据传输的错误。-8-channel to achieve high-speed analog data acquisition, high accuracy, using time-division multiplexing method, to avoid data transmission errors.
相关搜索： voltage_comp_verilog 数据传输 时分复用 VHDL

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下载文件列表

Voltage_Comp_Verilog/COMP_SM.v
Voltage_Comp_Verilog/constraint/
Voltage_Comp_Verilog/coreconsole/
Voltage_Comp_Verilog/designer/
Voltage_Comp_Verilog/designer/impl1/
Voltage_Comp_Verilog/designer/impl1/designer_genhdl.log
Voltage_Comp_Verilog/designer/impl1/simulation/
Voltage_Comp_Verilog/designer/impl1/TOP_CM.tcl
Voltage_Comp_Verilog/hdl/
Voltage_Comp_Verilog/hdl/COMP_SM.v
Voltage_Comp_Verilog/hdl/TOP_CM.v
Voltage_Comp_Verilog/phy_synthesis/
Voltage_Comp_Verilog/simulation/
Voltage_Comp_Verilog/simulation/AB_CM_acm_ram_R0C0.mem
Voltage_Comp_Verilog/simulation/AB_CM_assc_ram_R0C0.mem
Voltage_Comp_Verilog/simulation/AB_CM_smev_ram_R0C0.mem
Voltage_Comp_Verilog/simulation/AB_CM_smtr_ram_R0C0.mem
Voltage_Comp_Verilog/simulation/meminit.dat
Voltage_Comp_Verilog/simulation/modelsim.ini
Voltage_Comp_Verilog/simulation/modelsim.ini.sav
Voltage_Comp_Verilog/simulation/modelsim.log
Voltage_Comp_Verilog/simulation/NVM_CM.mem
Voltage_Comp_Verilog/simulation/presynth/
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m/
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_assc_ram/
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_assc_ram/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_assc_ram/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_assc_ram/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_assc_wrapper/
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_assc_wrapper/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_assc_wrapper/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_assc_wrapper/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smev_ram/
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smev_ram/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smev_ram/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smev_ram/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smev_wrapper/
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smev_wrapper/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smev_wrapper/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smev_wrapper/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smtr_ram/
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smtr_ram/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smtr_ram/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smtr_ram/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smtr_wrapper/
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smtr_wrapper/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smtr_wrapper/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@a@b_@c@m_smtr_wrapper/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@a@s@s@c/
Voltage_Comp_Verilog/simulation/presynth/@a@s@s@c/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@a@s@s@c/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@a@s@s@c/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@c@o@m@p_@s@m/
Voltage_Comp_Verilog/simulation/presynth/@c@o@m@p_@s@m/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@c@o@m@p_@s@m/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@c@o@m@p_@s@m/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g/
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@a/
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@a/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@a/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@a/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@b/
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@b/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@b/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@b/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@c/
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@c/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@c/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@c/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@d/
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@d/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@d/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@d/_primary.vhd
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@e/
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@e/verilog.psm
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@e/_primary.dat
Voltage_Comp_Verilog/simulation/presynth/@i@n@i@t@c@f@g_@x@e/_primary.vhd
Voltage

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