文件名称:uart_rxd
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- 上传时间:2012-11-16
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文件大小:1.66mb
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基于verilog hdl的UART串口接收子程序。-Verilog hdl a UART-based serial port to receive subroutine.
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下载文件列表
uart_rxd/db/prev_cmp_uart_rxd.asm.qmsg
uart_rxd/db/prev_cmp_uart_rxd.eda.qmsg
uart_rxd/db/prev_cmp_uart_rxd.fit.qmsg
uart_rxd/db/prev_cmp_uart_rxd.map.qmsg
uart_rxd/db/prev_cmp_uart_rxd.qmsg
uart_rxd/db/prev_cmp_uart_rxd.tan.qmsg
uart_rxd/db/uart_rxd.(0).cnf.cdb
uart_rxd/db/uart_rxd.(0).cnf.hdb
uart_rxd/db/uart_rxd.asm.qmsg
uart_rxd/db/uart_rxd.asm_labs.ddb
uart_rxd/db/uart_rxd.cbx.xml
uart_rxd/db/uart_rxd.cmp.bpm
uart_rxd/db/uart_rxd.cmp.cdb
uart_rxd/db/uart_rxd.cmp.ecobp
uart_rxd/db/uart_rxd.cmp.hdb
uart_rxd/db/uart_rxd.cmp.kpt
uart_rxd/db/uart_rxd.cmp.logdb
uart_rxd/db/uart_rxd.cmp.rdb
uart_rxd/db/uart_rxd.cmp.tdb
uart_rxd/db/uart_rxd.cmp0.ddb
uart_rxd/db/uart_rxd.cmp2.ddb
uart_rxd/db/uart_rxd.cmp_merge.kpt
uart_rxd/db/uart_rxd.db_info
uart_rxd/db/uart_rxd.eco.cdb
uart_rxd/db/uart_rxd.eda.qmsg
uart_rxd/db/uart_rxd.fit.qmsg
uart_rxd/db/uart_rxd.hier_info
uart_rxd/db/uart_rxd.hif
uart_rxd/db/uart_rxd.lpc.html
uart_rxd/db/uart_rxd.lpc.rdb
uart_rxd/db/uart_rxd.lpc.txt
uart_rxd/db/uart_rxd.map.bpm
uart_rxd/db/uart_rxd.map.cdb
uart_rxd/db/uart_rxd.map.ecobp
uart_rxd/db/uart_rxd.map.hdb
uart_rxd/db/uart_rxd.map.kpt
uart_rxd/db/uart_rxd.map.logdb
uart_rxd/db/uart_rxd.map.qmsg
uart_rxd/db/uart_rxd.map_bb.cdb
uart_rxd/db/uart_rxd.map_bb.hdb
uart_rxd/db/uart_rxd.map_bb.logdb
uart_rxd/db/uart_rxd.pre_map.cdb
uart_rxd/db/uart_rxd.pre_map.hdb
uart_rxd/db/uart_rxd.rtlv.hdb
uart_rxd/db/uart_rxd.rtlv_sg.cdb
uart_rxd/db/uart_rxd.rtlv_sg_swap.cdb
uart_rxd/db/uart_rxd.sgdiff.cdb
uart_rxd/db/uart_rxd.sgdiff.hdb
uart_rxd/db/uart_rxd.sld_design_entry.sci
uart_rxd/db/uart_rxd.sld_design_entry_dsc.sci
uart_rxd/db/uart_rxd.syn_hier_info
uart_rxd/db/uart_rxd.tan.qmsg
uart_rxd/db/uart_rxd.tis_db_list.ddb
uart_rxd/db/uart_rxd.tmw_info
uart_rxd/db/uart_rxd_global_asgn_op.abo
uart_rxd/db/wed.wsf
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.atm
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.dfp
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.hdbx
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.kpt
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.logdb
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.rcf
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.map.atm
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.map.dpi
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.map.hdbx
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.map.kpt
uart_rxd/incremental_db/README
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i@i_@p@r@i@m_@d@f@f@e/verilog.psm
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i@i_@p@r@i@m_@d@f@f@e/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/verilog.psm
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.psm
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.dat
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and1/verilog.psm
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and1/_primary.dat
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and1/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and1/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and16/verilog.psm
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and16/_primary.dat
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and16/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and16/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cycloneiii_apfcontroller/verilog.psm
uart_rxd/simulation/modelsim/gate_work/cycloneiii_apfcontroller/_primary.dat
uart_rxd/simulation/modelsim/gate_work/cycloneiii_apfcontroller/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/cycloneiii_apfcontroller/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b17mux21/verilog.psm
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b17mux21/_primary.dat
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b17mux21/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b17mux21/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b5mux21/verilog.psm
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b5mux21/_primary.dat
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b5mux21/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b5mux21/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cyclone
uart_rxd/db/prev_cmp_uart_rxd.eda.qmsg
uart_rxd/db/prev_cmp_uart_rxd.fit.qmsg
uart_rxd/db/prev_cmp_uart_rxd.map.qmsg
uart_rxd/db/prev_cmp_uart_rxd.qmsg
uart_rxd/db/prev_cmp_uart_rxd.tan.qmsg
uart_rxd/db/uart_rxd.(0).cnf.cdb
uart_rxd/db/uart_rxd.(0).cnf.hdb
uart_rxd/db/uart_rxd.asm.qmsg
uart_rxd/db/uart_rxd.asm_labs.ddb
uart_rxd/db/uart_rxd.cbx.xml
uart_rxd/db/uart_rxd.cmp.bpm
uart_rxd/db/uart_rxd.cmp.cdb
uart_rxd/db/uart_rxd.cmp.ecobp
uart_rxd/db/uart_rxd.cmp.hdb
uart_rxd/db/uart_rxd.cmp.kpt
uart_rxd/db/uart_rxd.cmp.logdb
uart_rxd/db/uart_rxd.cmp.rdb
uart_rxd/db/uart_rxd.cmp.tdb
uart_rxd/db/uart_rxd.cmp0.ddb
uart_rxd/db/uart_rxd.cmp2.ddb
uart_rxd/db/uart_rxd.cmp_merge.kpt
uart_rxd/db/uart_rxd.db_info
uart_rxd/db/uart_rxd.eco.cdb
uart_rxd/db/uart_rxd.eda.qmsg
uart_rxd/db/uart_rxd.fit.qmsg
uart_rxd/db/uart_rxd.hier_info
uart_rxd/db/uart_rxd.hif
uart_rxd/db/uart_rxd.lpc.html
uart_rxd/db/uart_rxd.lpc.rdb
uart_rxd/db/uart_rxd.lpc.txt
uart_rxd/db/uart_rxd.map.bpm
uart_rxd/db/uart_rxd.map.cdb
uart_rxd/db/uart_rxd.map.ecobp
uart_rxd/db/uart_rxd.map.hdb
uart_rxd/db/uart_rxd.map.kpt
uart_rxd/db/uart_rxd.map.logdb
uart_rxd/db/uart_rxd.map.qmsg
uart_rxd/db/uart_rxd.map_bb.cdb
uart_rxd/db/uart_rxd.map_bb.hdb
uart_rxd/db/uart_rxd.map_bb.logdb
uart_rxd/db/uart_rxd.pre_map.cdb
uart_rxd/db/uart_rxd.pre_map.hdb
uart_rxd/db/uart_rxd.rtlv.hdb
uart_rxd/db/uart_rxd.rtlv_sg.cdb
uart_rxd/db/uart_rxd.rtlv_sg_swap.cdb
uart_rxd/db/uart_rxd.sgdiff.cdb
uart_rxd/db/uart_rxd.sgdiff.hdb
uart_rxd/db/uart_rxd.sld_design_entry.sci
uart_rxd/db/uart_rxd.sld_design_entry_dsc.sci
uart_rxd/db/uart_rxd.syn_hier_info
uart_rxd/db/uart_rxd.tan.qmsg
uart_rxd/db/uart_rxd.tis_db_list.ddb
uart_rxd/db/uart_rxd.tmw_info
uart_rxd/db/uart_rxd_global_asgn_op.abo
uart_rxd/db/wed.wsf
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.atm
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.dfp
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.hdbx
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.kpt
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.logdb
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.cmp.rcf
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.map.atm
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.map.dpi
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.map.hdbx
uart_rxd/incremental_db/compiled_partitions/uart_rxd.root_partition.map.kpt
uart_rxd/incremental_db/README
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i@i_@p@r@i@m_@d@f@f@e/verilog.psm
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i@i_@p@r@i@m_@d@f@f@e/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/verilog.psm
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.psm
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.dat
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and1/verilog.psm
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and1/_primary.dat
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and1/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and1/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and16/verilog.psm
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and16/_primary.dat
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and16/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/cycloneiii_and16/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cycloneiii_apfcontroller/verilog.psm
uart_rxd/simulation/modelsim/gate_work/cycloneiii_apfcontroller/_primary.dat
uart_rxd/simulation/modelsim/gate_work/cycloneiii_apfcontroller/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/cycloneiii_apfcontroller/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b17mux21/verilog.psm
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b17mux21/_primary.dat
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b17mux21/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b17mux21/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b5mux21/verilog.psm
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b5mux21/_primary.dat
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b5mux21/_primary.dbs
uart_rxd/simulation/modelsim/gate_work/cycloneiii_b5mux21/_primary.vhd
uart_rxd/simulation/modelsim/gate_work/cyclone
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