介绍Verilog HDL, 内容包括：

– Verilog应用

– Verilog语言的构成元素

– 结构级描述及仿真

– 行为级描述及仿真

– 延时的特点及说明

– 介绍Verilog testbench

• 激励和控制和描述

• 结果的产生及验证

– 任务task及函数function

– 用户定义的基本单元(primitive)

– 可综合的Verilog描述风格-Introduced the Verilog HDL, including:- Verilog applications- Verilog language constitute elements- structural level descr iption and simulation- behavioral descr iption and simulation- and describe the characteristics of delay- to introduce incentives and Verilog testbench •　•　the results of control and described the emergence and Authentication- the task function task and function- the basic unit of user-defined (primitive)- can be integrated to describe the style of Verilog