应用VHDL语言设计数字系统，很多设计工作可以在计算机上完成，从而缩短了系统的开发时间，提高了工作效率。本文介绍一种以FPGA为核心，以VHDL为开发工具的数字秒表，并给出源程序和仿真结果。

-Application of VHDL language design digital systems, a lot of design work can be completed on the computer, thereby reducing system development time and improve efficiency. This article describes an FPGA as the core, a tool for the development of VHDL digital stopwatch, and the source code and simulation results are given.